diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2018-07-18 11:48:47 +0200 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2018-10-15 14:10:18 +0000 |
commit | 1541256f22bbb046a43ccebf73d994d4f4a53374 (patch) | |
tree | f3fbbf0a870b5462b51e9347c91550146f54db13 /src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl | |
parent | 6db1b2fc24e5634d139d34c93813c2f703583494 (diff) |
mb/asus/p5qc: Add mainboard
SeaBIOS does not seem to like the Marvel IDE controller, so disabled SeaBIOS
support for ATA. It works fine in Linux afterwards.
Working:
- SATA on southbridge port
- SATA on marvel IDE controller ports (only in Linux)
- USB
- COM1
- PS2 Keyboard
- DDR2 DIMMs
- PCIe x16 PEG port
- PCI port
- NIC (needs a driver to set macaddress)
- S3 resume
Not working:
- SeaBIOS with ATA support (long timeout marvel controller so disabled)
- DDR3 fails because the proper clock signal does not get enabled. Even when
fixing this it fails later or during memtest, so it should be considered
unsupported for now
Untested:
- PCIe x1 ports (expected to work)
- sound (expected to work)
TODO:
add documentation
Change-Id: I4a81940707566776bd048904ca1387fea741fece
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl')
-rw-r--r-- | src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl b/src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl new file mode 100644 index 0000000000..e8cb26eb65 --- /dev/null +++ b/src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH10 + */ + +If (PICM) { + Return (Package() { + /* PCI slot */ + Package() { 0x0000ffff, 0, 0, 0x10}, + Package() { 0x0000ffff, 1, 0, 0x11}, + Package() { 0x0000ffff, 2, 0, 0x12}, + Package() { 0x0000ffff, 3, 0, 0x13}, + + Package() { 0x0001ffff, 0, 0, 0x11}, + Package() { 0x0001ffff, 1, 0, 0x12}, + Package() { 0x0001ffff, 2, 0, 0x13}, + Package() { 0x0001ffff, 3, 0, 0x10}, + + Package() { 0x0002ffff, 0, 0, 0x12}, + Package() { 0x0002ffff, 1, 0, 0x13}, + Package() { 0x0002ffff, 2, 0, 0x10}, + Package() { 0x0002ffff, 3, 0, 0x11}, + + Package() { 0x0003ffff, 0, 0, 0x13}, + }) +} Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKB, 0}, + + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKD, 0}, + }) +} |