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authorFrans Hendriks <fhendriks@eltan.com>2018-10-31 13:58:26 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-11-28 11:49:35 +0000
commit190e5bee4a75208d1975c639321f46d4425e3583 (patch)
treecc89ddff3b8ab6793515ec30ab49e3ae1fb2ec01 /src/mainboard/asus/p5qc/Kconfig.name
parent624195e45423d854f350386803544624b1b976c3 (diff)
src/soc/intel/braswell/include/soc/irq.h: Change PIRQ_PIC_IRQDISABLE value
Using 0 for PIRQ_PIC_IRQDISABLE might conflict with using IRQ0 as PIRQ. Change PIRQ_PIC_IRQDISABLE value to 0x80, so value 0 is reserved for IRQ0. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I18706f12e7c2293e948eb10818393f0d1870f514 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29393 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asus/p5qc/Kconfig.name')
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