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author | V Sowmya <v.sowmya@intel.com> | 2019-04-02 18:55:15 +0530 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-04 10:34:28 +0000 |
commit | e8c655dd1b2490e24640ebafb16120e5e9c268f3 (patch) | |
tree | e9024acbbb7b60f2c5f49b58f0f302c66d9cce3c /src/mainboard/asus/p5gc-mx | |
parent | c10fed07432be9fc5e4f077ca567b749a56c8f48 (diff) |
mb/intel/coffeelake_rvp: Configure FSP UPDs of DDI ports for cmlrvp
This patch configures FSP UPD values for HPD and DDC of DDI ports for
CMLRVP.
BUG=none
TEST= Tested that eDP works on CMLRVP.
Change-Id: If8c8480eaf2d63cec0b5598b5af3088c630dd78a
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32140
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asus/p5gc-mx')
0 files changed, 0 insertions, 0 deletions