diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2016-12-30 18:52:53 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-01-03 17:42:22 +0100 |
| commit | 87fff20356466887d5e879ded540862087e09580 (patch) | |
| tree | 54c22e31baa1ab3c48a852b1a0f101f36c0e7147 /src/mainboard/asus/p5gc-mx | |
| parent | de47fc3317ce34abd91cc2be11827c96ae9bc1f8 (diff) | |
mb/asus/p5gc-mx: Remove extra BSEL strap check
This extra check is based on comparing CPU BSEL pins and reports in
MCH configuration. This gives false positives in the case of 1333MHz
CPUs which automatically get downgraded to 1067MHz by the northbridge
(max supported frequency by 945gc).
TESTED with Intel Xeon 5460 (does not boot but completes raminit)
Change-Id: I34cb37912906c803abdad0adbd9c589ca86a67c7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17997
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/asus/p5gc-mx')
| -rw-r--r-- | src/mainboard/asus/p5gc-mx/romstage.c | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index 9be061f0a8..8785595da4 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -242,12 +242,7 @@ void mainboard_romstage_entry(unsigned long bist) i945_early_initialization(); m_bsel = MCHBAR32(CLKCFG) & 7; - printk(BIOS_DEBUG, "CPU BSEL: 0x%x\n MCH BSEL: 0x%x\n", c_bsel, m_bsel); - if (c_bsel != m_bsel) { /* Should not happen */ - printk(BIOS_DEBUG, "Setting BSEL straps, resetting...\n"); - outb(0xe, 0xcf9); - halt(); - } + printk(BIOS_DEBUG, "CPU BSEL: 0x%x\nMCH BSEL: 0x%x\n", c_bsel, m_bsel); s3resume = southbridge_detect_s3_resume(); |