diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-01-06 20:01:57 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-01-06 20:23:07 +0100 |
| commit | 8f8d56dded9a9fcf5af64996fde946cf372755f2 (patch) | |
| tree | 9dec8c27d8e0b9cbeebd76246740867d83ea8e77 /src/mainboard/asus/p5gc-mx/romstage.c | |
| parent | b5623dede7569cf74dd865748d17b0e413c03ee2 (diff) | |
mb/asus/p5gc-mx: Use common/gpio.h
Should have been included in 62902ca45d "sb/ich7: Use common/gpio.h to
set up GPIOs", which was not rebased on addition of this board.
Change-Id: If4547ee43ce6a7a6e4af67e9364613e48f989401
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18047
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/asus/p5gc-mx/romstage.c')
| -rw-r--r-- | src/mainboard/asus/p5gc-mx/romstage.c | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index f0c48a3700..efeaaec7e8 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -44,23 +44,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) -void setup_ich7_gpios(void) -{ - /* TODO: This is highly board specific and should be moved */ - printk(BIOS_DEBUG, " GPIOS..."); - /* General Registers */ - outl(0x1f3dffc1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ - outl(0xe0e8f7c2, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ - outl(0xe2febb7e, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ - /* Output Control Registers */ - outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ - /* Input Control Registers */ - outl(0x00006000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ - outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ - outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ - outl(0x00030033, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ -} - /* * BSEL0 is connected with GPIO32 * BSEL1 is connected with GPIO33 with inversed logic |