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| author | Michael Niewöhner <foss@mniewoehner.de> | 2019-11-02 12:14:06 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-11 10:26:14 +0000 |
| commit | e919390f4735a762234630ab7e0807c14de45421 (patch) | |
| tree | 00a607d365f06c75fc7f34ee7ef8a2c6b0d0f042 /src/mainboard/asus/p5gc-mx/cstates.c | |
| parent | 93d215cb05a05464fef14f26f638341da2ce3d59 (diff) | |
soc/intel/icelake: add soc implementation for ETR address API
Add soc implementation for the new ETR address API.
Change-Id: I8383a60c2c4988948ab8b3e9a54330269d217868
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36568
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asus/p5gc-mx/cstates.c')
0 files changed, 0 insertions, 0 deletions