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| author | Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> | 2024-11-19 11:18:37 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-11-26 05:51:19 +0000 |
| commit | 80caf690d01165e1e395b281b2c14c1057c3598e (patch) | |
| tree | 4022f0a0c8eeb7850b8053a020d6ca702c155461 /src/mainboard/asus/p5gc-mx/cmos.layout | |
| parent | 73a1f02592bd8c8759b97628cfafafd542c31748 (diff) | |
mb/google/brya/var/trulo: Remove overriding of PL1 value to 20W
The RAPL PL1 limit and MMIO PL1 max values should be set as per
silicon TDP as specified in the PDG doc#646929.
BUG=b:378623372
TEST=Build and boot on Trulo board.
Verified PL1 value is updated in DTT and sysfs interfaces.
Output with 15W silicon as below:
cd /sys/class/powercap/
cat intel-rapl/intel-rapl\:0/constraint_0_max_power_uw
15000000
cat intel-rapl/intel-rapl\:0/constraint_0_power_limit_uw
15000000
cat intel-rapl-mmio/intel-rapl-mmio\:0/constraint_0_max_power_uw
15000000
cat intel-rapl-mmio/intel-rapl-mmio\:0/constraint_0_power_limit_uw
15000000
Change-Id: I798c4f10e10a579f470e00dbdb77a84619ad796a
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85184
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src/mainboard/asus/p5gc-mx/cmos.layout')
0 files changed, 0 insertions, 0 deletions