diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-07 13:52:11 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2023-01-30 10:49:11 +0000 |
| commit | 69cd729c0cde6f15d1de692f5a2da5d3dfe8ba15 (patch) | |
| tree | 4f21a3de147f422336545ed3164581b6b80c45d7 /src/mainboard/asus/p2b/variants | |
| parent | 0a97e466163dda4e55c1eda145646054dcd8dd06 (diff) | |
mb/*: Remove lapic from devicetree
The parallel mp code picks up lapics at runtime, so remove it from all
devicetrees that use this codebase.
Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/asus/p2b/variants')
| -rw-r--r-- | src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb | 6 | ||||
| -rw-r--r-- | src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb | 6 |
2 files changed, 0 insertions, 12 deletions
diff --git a/src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb b/src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb index ce36ce60d0..ed6224fbd7 100644 --- a/src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb +++ b/src/mainboard/asus/p2b/variants/p2b-d/overridetree.cb @@ -1,11 +1,5 @@ chip northbridge/intel/i440bx # Northbridge device cpu_cluster 0 on # (L)APIC cluster - chip cpu/intel/slot_1 # CPU socket 0 - device lapic 0 on end # Local APIC of CPU 0 - end - chip cpu/intel/slot_1 # CPU socket 1 - device lapic 1 on end # Local APIC of CPU 1 - end end device domain 0 on # PCI domain chip southbridge/intel/i82371eb # Southbridge diff --git a/src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb b/src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb index b261a3514f..adcce28057 100644 --- a/src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb +++ b/src/mainboard/asus/p2b/variants/p2b-ds/overridetree.cb @@ -1,11 +1,5 @@ chip northbridge/intel/i440bx # Northbridge device cpu_cluster 0 on # (L)APIC cluster - chip cpu/intel/slot_1 # CPU socket 0 - device lapic 0 on end # Local APIC of CPU 0 - end - chip cpu/intel/slot_1 # CPU socket 1 - device lapic 1 on end # Local APIC of CPU 1 - end end device domain 0 on # PCI domain chip southbridge/intel/i82371eb # Southbridge |