diff options
author | Keith Hui <buurin@gmail.com> | 2020-04-19 00:55:48 -0400 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-11 09:33:23 +0000 |
commit | edd38465a58d47b737f1e656a8055f64a3b0c421 (patch) | |
tree | c070c8409efa9728c132b6ad114f1aa628cd6c71 /src/mainboard/asus/p2b/variants/p3b-f/romstage.c | |
parent | 75476ec3038497871741519c59ee2bfe3463e14b (diff) |
mainboard/asus/p3b-f: Reintroduce as variant of p2b
Fold this last ASUS 440BX board into the P2B family, while bringing in
some changes:
- Devicetree becomes overridetree.
- Remove non-existent IR device and disable ACPI device on Super I/O to
match OEM firmware.
- Add SB GPO settings from OEM firmware to devicetree. This disables
the SPD enabling magic this board needs. By moving the enabling part
to bootblock the hacky enable_spd hook can be eliminated.
- Initialize the serial port in bootblock, like the other boards.
Boot tested on hardware.
Change-Id: I65f2cb9d1bd4c82550de43889e3502526a46bd18
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41047
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asus/p2b/variants/p3b-f/romstage.c')
-rw-r--r-- | src/mainboard/asus/p2b/variants/p3b-f/romstage.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/src/mainboard/asus/p2b/variants/p3b-f/romstage.c b/src/mainboard/asus/p2b/variants/p3b-f/romstage.c new file mode 100644 index 0000000000..437a38fded --- /dev/null +++ b/src/mainboard/asus/p2b/variants/p3b-f/romstage.c @@ -0,0 +1,37 @@ +/* This file is part of the coreboot project. */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <arch/io.h> +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> + +/* + * ASUS P3B-F specific SPD enable magic. + * + * Setting the byte at offset 0x37 in the PM I/O space to 0x6f will make the + * board DIMMs accessible at SMBus/SPD offsets 0x50-0x53. Per default the SPD + * offsets 0x50-0x53 are _not_ readable (all SPD reads will return 0xff) which + * will make RAM init fail. + * + * Tested values for PM I/O offset 0x37: + * 0x67: 11 00 111: Only SMBus/I2C offsets 0x48/0x49/0x2d accessible + * 0x6f: 11 01 111: Only SMBus/I2C offsets 0x50-0x53 (SPD) accessible + * 0x77: 11 10 111: Only SMBus/I2C offset 0x69 accessible + * + * PM I/O space offset 0x37 is GPOREG[31:24], i.e. it controls the GPIOs + * 24-30 of the PIIX4E (bit 31 is reserved). Thus, GPIOs 27 and 28 + * control which SMBus/I2C offsets can be accessed. + */ +void enable_spd(void) +{ + outb(0x6f, PM_IO_BASE + 0x37); +} + +/* + * Disable SPD access after RAM init to allow access to SMBus/I2C offsets + * 0x48/0x49/0x2d, which is required e.g. by lm-sensors. + */ +void disable_spd(void) +{ + outb(0x67, PM_IO_BASE + 0x37); +} |