- Add support _framework_ for the Asus p2b.

- New superIO winbond/w83977tf
- Add single memory controller SBbus debug routine
into a file private to the i440bx

This adds support the start of support for an Asus p2b
mainboard.  Current limitations are the same as for the 
Bitworks IMS board.  Reads from the SMbus don't work.

Moving dump_spd_registers() into its own private copy
solves the problem of having to go hack on the version that
included in src/sdram to only do one memory controller.




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 32 insertions, 0 deletions

diff --git a/src/mainboard/asus/p2b/irq_tables.c b/src/mainboard/asus/p2b/irq_tables.c
new file mode 100644
index 0000000000..894c27dec5
--- /dev/null
+++ b/src/mainboard/asus/p2b/irq_tables.c
@@ -0,0 +1,32 @@
+/* This file was generated by getpir.c, do not modify! 
+   (but if you do, please run checkpir on it to verify)
+   Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
+
+   Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE, /* u32 signature */
+	PIRQ_VERSION,   /* u16 version   */
+	32+16*5,        /* there can be total 5 devices on the bus */
+	0,              /* Where the interrupt router lies (bus) */
+	0x88,           /* Where the interrupt router lies (dev) */
+	0x1c20,         /* IRQs devoted exclusively to PCI usage */
+	0x1106,         /* Vendor */
+	0x8231,         /* Device */
+	0,              /* Crap (miniport) */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x5e,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+	{
+		/* 8231 ethernet */
+		{0,0x90, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x1, 0},
+		/* 8231 internal */
+		{0,0x88, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0},
+		/* PCI slot */
+		{0,0xa0, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}}, 0, 0},
+		{0,0x50, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0},
+		{0,0x98, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
+	}
+};