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authorSubrata Banik <subrata.banik@intel.com>2016-08-19 12:33:42 +0530
committerAaron Durbin <adurbin@chromium.org>2016-10-16 02:50:26 +0200
commitff8bf410d9596ac82b183cb62e2d8990c550ee4a (patch)
tree30ff1c100dcb1a4e0a91db6eb3e3a5aa6e185ba1 /src/mainboard/asus/p2b-d/Kconfig
parent29f8708fca820797a088c7e81eb830fc61b21d28 (diff)
soc/intel/skylake: Implement Global Reset MEI message
As per ME BWG, there are two mechanism to generate a Global Reset (resets both host and Intel ME), one is through CF9h IO write of 6h or Eh with "CF9h Global Reset" (CF9GR) bit set, PMC PCI offset ACh[20]. Another is to issue the Global Reset MEI message. Because any attempts to cause global reset without synchronizing the two sides might cause unwanted side effects, such as unwritten flash data that will get destroyed if the host were to cause a global reset without informing Intel ME firmware, the recommended method is to send a Global Reset MEI message when the following conditions are met: The PCH chipset firmware just needs to complete the Intel ME Interface #1 initialization and check the Intel ME HFSTS state if Intel ME is not in ERROR state and is accepting MEI commands then firmware should be able to use Global Reset MEI message to trigger global reset. Furthermore, if Intel ME is in ERROR state, BIOS can use I/O 0xCF9 write of 0x06 or 0x0E command with PCH ETR3 register bit [20] to perform the global reset. BUG=none BRANCH=none TEST=Verified Global Reset MEI message is able to perform platform global issue in ME good state. Change-Id: If326a137eeadaa695668b76b84c510e12c546024 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16902 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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