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authorElyes HAOUAS <ehaouas@noos.fr>2016-09-16 20:49:38 +0200
committerPatrick Georgi <pgeorgi@google.com>2016-09-20 19:06:28 +0200
commit6350a2e43f3657567f50160aa28d5d4305803be0 (patch)
tree66473657856456754ab78a636c393c1a744932be /src/mainboard/asus/mew-vm
parented5f159ed59c52a4731d07ef19bff8ef8de9ae14 (diff)
src/mainboard/a-trend - emulation: Add space around operators
Change-Id: Ib00a9b2feb723d46642d86b2706728bbca7dd68d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16616 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/asus/mew-vm')
-rw-r--r--src/mainboard/asus/mew-vm/irq_tables.c26
1 files changed, 13 insertions, 13 deletions
diff --git a/src/mainboard/asus/mew-vm/irq_tables.c b/src/mainboard/asus/mew-vm/irq_tables.c
index 3d8bebe242..7ebc2d53d6 100644
--- a/src/mainboard/asus/mew-vm/irq_tables.c
+++ b/src/mainboard/asus/mew-vm/irq_tables.c
@@ -5,7 +5,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_VERSION, /* u16 version */
32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
- (0x11<<3)|0x0, /* Where the interrupt router lies (dev) */
+ (0x11 << 3)|0x0, /* Where the interrupt router lies (dev) */
0xe20, /* IRQs devoted exclusively to PCI usage */
0x8086, /* Vendor */
0x7120, /* Device */
@@ -14,18 +14,18 @@ static const struct irq_routing_table intel_irq_routing_table = {
0x89, /* u8 checksum , this has to set to some value
that would give 0 after the sum of all bytes for this structure (including checksum) */
{
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x08<<3)|0x0, {{0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0xdea0}, {0x01, 0x0dea0}}, 0x1, 0x0},
- {0x00,(0x09<<3)|0x0, {{0x03, 0xdea0}, {0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0x0dea0}}, 0x2, 0x0},
- {0x00,(0x0a<<3)|0x0, {{0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0x0dea0}}, 0x3, 0x0},
- {0x00,(0x0b<<3)|0x0, {{0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0x0dea0}}, 0x4, 0x0},
- {0x00,(0x0c<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x5, 0x0},
- {0x00,(0x0d<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x6, 0x0},
- {0x00,(0x11<<3)|0x0, {{0x00, 0xdea0}, {0x00, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0},
- {0x00,(0x0f<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0},
- {0x00,(0x01<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0},
- {0x00,(0x10<<3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0},
- {0x00,(0x12<<3)|0x0, {{0x01, 0xdea0}, {0x00, 0xdea0}, {0x00, 0xdea0}, {0x00, 0x0dea0}}, 0x0, 0x0},
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00,(0x08 << 3)|0x0, {{0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0xdea0}, {0x01, 0x0dea0}}, 0x1, 0x0},
+ {0x00,(0x09 << 3)|0x0, {{0x03, 0xdea0}, {0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0x0dea0}}, 0x2, 0x0},
+ {0x00,(0x0a << 3)|0x0, {{0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0x0dea0}}, 0x3, 0x0},
+ {0x00,(0x0b << 3)|0x0, {{0x04, 0xdea0}, {0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0x0dea0}}, 0x4, 0x0},
+ {0x00,(0x0c << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x5, 0x0},
+ {0x00,(0x0d << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x6, 0x0},
+ {0x00,(0x11 << 3)|0x0, {{0x00, 0xdea0}, {0x00, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0},
+ {0x00,(0x0f << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0},
+ {0x00,(0x01 << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0},
+ {0x00,(0x10 << 3)|0x0, {{0x01, 0xdea0}, {0x02, 0xdea0}, {0x03, 0xdea0}, {0x04, 0x0dea0}}, 0x0, 0x0},
+ {0x00,(0x12 << 3)|0x0, {{0x01, 0xdea0}, {0x00, 0xdea0}, {0x00, 0xdea0}, {0x00, 0x0dea0}}, 0x0, 0x0},
}
};