diff options
author | QingPei Wang <wangqingpei@gmail.com> | 2011-09-13 17:54:12 +0800 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-10-28 22:26:07 +0200 |
commit | cc66d97f505c304e773dea938ac864cd74363292 (patch) | |
tree | 2e19f47aa4435b07c4c3e148a3d12adf3558a080 /src/mainboard/asus/m5a88-v/fadt.c | |
parent | 914377efd61be7b473faca0e6bdfca6f3feb5dc5 (diff) |
Add ASUS M5A88-V mainboard support
it's a AMD 880+800 mainboard. I port the code
based on the AMD reference code.
update: 1.use CIMX instead of pmio
2.fix some whitespace
3.fix subsystemid of devicetree.cb
Change-Id: I9725ccdbb25365c4007621318efee80b131fec29
Signed-off-by: QingPei Wang <wangqingpei@gmail.com>
Reviewed-on: http://review.coreboot.org/205
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/asus/m5a88-v/fadt.c')
-rw-r--r-- | src/mainboard/asus/m5a88-v/fadt.c | 189 |
1 files changed, 189 insertions, 0 deletions
diff --git a/src/mainboard/asus/m5a88-v/fadt.c b/src/mainboard/asus/m5a88-v/fadt.c new file mode 100644 index 0000000000..adba78055b --- /dev/null +++ b/src/mainboard/asus/m5a88-v/fadt.c @@ -0,0 +1,189 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + */ + +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <device/device.h> +#include "SBPLATFORM.h" + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + u16 val; + acpi_header_t *header = &(fadt->header); + + printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE); + + /* Prepare the header */ + memset((void *)fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (u32) facs; + fadt->dsdt = (u32) dsdt; + /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + fadt->preferred_pm_profile = 0x03; + fadt->sci_int = 9; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0; + fadt->acpi_enable = 0xf0; + fadt->acpi_disable = 0xf1; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + val = PM1_EVT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val); + val = PM1_CNT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val); + val = PM1_TMR_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val); + val = GPE0_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val); + + /* CpuControl is in \_PR.CPU0, 6 bytes */ + val = CPU_CNT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val); + val = 0; + WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val); + val = ACPI_PMA_CNT_BLK_ADDRESS; + WritePMIO(SB_PMIOA_REG6C, AccWidthUint16, &val); + + /* AcpiDecodeEnable, When set, SB uses the contents of the + * PM registers at index 60-6B to decode ACPI I/O address. + * AcpiSmiEn & SmiCmdEn + */ + val = BIT0 | BIT1 | BIT2 | BIT4; + WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val); + + /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ + + fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS; + fadt->gpe0_blk = GPE0_BLK_ADDRESS; + fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ + fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ + fadt->flags = 0x0001c1a5;/* 0x25; */ + + fadt->res2 = 0; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (u32) facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32) dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); +} |