mb/*/*: Drop AMDFAM10 mainboards

Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: Ic00ca18de3d73a17041a3a2839307149ad7902b2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36961 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
author: Arthur Heymans <arthur@aheymans.xyz> 2019-11-19 15:55:05 +0100
committer: Kyösti Mälkki <kyosti.malkki@gmail.com> 2019-11-20 18:58:43 +0000
commit: f2e42c4a8ec75c162251c72df8ac3da12e8a3eb9 (patch)
tree: fd5851ba2be3965df592355d02bce01f7dab0215 /src/mainboard/asus/m4a785-m
parent: ad983eeec76ecdb2aff4fb47baeee95ade012225 (diff)
19 files changed, 0 insertions, 3833 deletions
diff --git a/src/mainboard/asus/m4a785-m/Kconfig b/src/mainboard/asus/m4a785-m/Kconfig
deleted file mode 100644
index 22665efe72..0000000000
--- a/src/mainboard/asus/m4a785-m/Kconfig
+++ /dev/null
@@ -1,58 +0,0 @@
-if BOARD_ASUS_M4A785M
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select CPU_AMD_SOCKET_AM3
-	select DIMM_DDR2
-	select NORTHBRIDGE_AMD_AMDFAM10
-	select SOUTHBRIDGE_AMD_RS780
-	select SOUTHBRIDGE_AMD_SB700
-	select SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT
-	select SUPERIO_ITE_IT8712F
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
-	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
-	select LIFT_BSP_APIC_ID
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_1024
-	select ENABLE_APIC_EXT_ID
-	select GFXUMA
-
-config MAINBOARD_DIR
-	string
-	default asus/m4a785-m
-
-config APIC_ID_OFFSET
-	hex
-	default 0x0
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "M4A785-M"
-
-config MAX_CPUS
-	int
-	default 8
-
-config MAX_PHYSICAL_CPUS
-	int
-	default 2
-
-config HT_CHAIN_END_UNITID_BASE
-	hex
-	default 0x1
-
-config HT_CHAIN_UNITID_BASE
-	hex
-	default 0x0
-
-config IRQ_SLOT_COUNT
-	int
-	default 19
-
-config VGA_BIOS_ID
-	string
-	default "1002,9710"
-
-endif
diff --git a/src/mainboard/asus/m4a785-m/Kconfig.name b/src/mainboard/asus/m4a785-m/Kconfig.name
deleted file mode 100644
index 1ab150ffb3..0000000000
--- a/src/mainboard/asus/m4a785-m/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASUS_M4A785M
-	bool "M4A785-M"
diff --git a/src/mainboard/asus/m4a785-m/Makefile.inc b/src/mainboard/asus/m4a785-m/Makefile.inc
deleted file mode 100644
index 91d4b39c32..0000000000
--- a/src/mainboard/asus/m4a785-m/Makefile.inc
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-romstage-y += resourcemap.c
-
-ramstage-y += get_bus_conf.c
diff --git a/src/mainboard/asus/m4a785-m/acpi/cpstate.asl b/src/mainboard/asus/m4a785-m/acpi/cpstate.asl
deleted file mode 100644
index acaa5bae32..0000000000
--- a/src/mainboard/asus/m4a785-m/acpi/cpstate.asl
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* This file defines the processor and performance state capability
- * for each core in the system.  It is included into the DSDT for each
- * core.  It assumes that each core of the system has the same performance
- * characteristics.
-*/
-/*
-#include <arch/acpi.h>
-DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001)
-	{
-	Scope (\_PR) {
-		Device (CPU0) {
-		Name (_HID, "ACPI0007")
-		Name (_UID, 0)
-			#include "cpstate.asl"
-		}
-		Device (CPU1) {
-		Name (_HID, "ACPI0007")
-		Name (_UID, 1)
-			#include "cpstate.asl"
-		}
-		Device (CPU2) {
-		Name (_HID, "ACPI0007")
-		Name (_UID, 2)
-			#include "cpstate.asl"
-		}
-		Device (CPU3) {
-		Name (_HID, "ACPI0007")
-		Name (_UID, 3)
-			#include "cpstate.asl"
-		}
-	}
-*/
-	/* P-state support: The maximum number of P-states supported by the */
-	/* CPUs we'll use is 6. */
-	/* Get from AMI BIOS. */
-	Name(_PSS, Package(){
-		Package ()
-		{
-		    0x00000AF0,
-		    0x0000BF81,
-		    0x00000002,
-		    0x00000002,
-		    0x00000000,
-		    0x00000000
-		},
-
-		Package ()
-		{
-		    0x00000578,
-		    0x000076F2,
-		    0x00000002,
-		    0x00000002,
-		    0x00000001,
-		    0x00000001
-		}
-	})
-
-	Name(_PCT, Package(){
-		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
-		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
-	})
-
-	Method(_PPC, 0){
-		Return(0)
-	}
diff --git a/src/mainboard/asus/m4a785-m/acpi/ide.asl b/src/mainboard/asus/m4a785-m/acpi/ide.asl
deleted file mode 100644
index 5c155cf301..0000000000
--- a/src/mainboard/asus/m4a785-m/acpi/ide.asl
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(IDEC) {
-			Name(_ADR, 0x00140001)
-			#include "ide.asl"
-		}
-	}
-}
-*/
-
-/* Some timing tables */
-Name(UDTT, Package(){ /* Udma timing table */
-	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
-})
-
-Name(MDTT, Package(){ /* MWDma timing table */
-	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(POTT, Package(){ /* Pio timing table */
-	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
-})
-
-/* Some timing register value tables */
-Name(MDRT, Package(){ /* MWDma timing register table */
-	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
-})
-
-Name(PORT, Package(){
-	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
-})
-
-OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
-	Field(ICRG, AnyAcc, NoLock, Preserve)
-{
-	PPTS, 8,	/* Primary PIO Slave Timing */
-	PPTM, 8,	/* Primary PIO Master Timing */
-	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
-	PMTM, 8,	/* Primary MWDMA Master Timing */
-	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
-	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
-	PPSM, 4,	/* Primary PIO slave Mode */
-	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
-	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
-	PDSM, 4,	/* Primary UltraDMA Mode */
-}
-
-Method(GTTM, 1) /* get total time*/
-{
-	Store(And(Arg0, 0x0F), Local0)	/* Recovery Width */
-	Increment(Local0)
-	Store(ShiftRight(Arg0, 4), Local1)	/* Command Width */
-	Increment(Local1)
-	Return(Multiply(30, Add(Local0, Local1)))
-}
-
-Device(PRID)
-{
-	Name (_ADR, Zero)
-	Method(_GTM, 0)
-	{
-		NAME(OTBF, Buffer(20) { /* out buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
-		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
-		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
-
-		/* Just return if the channel is disabled */
-		If(And(PPCR, 0x01)) { /* primary PIO control */
-			Return(OTBF)
-		}
-
-		/* Always tell them independent timing available and IOChannelReady used on both drives */
-		Or(BFFG, 0x1A, BFFG)
-
-		Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming  to PIO spd0 */
-		Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing  to PIO spd1 */
-
-		If(And(PDCR, 0x01)) {	/* It's under UDMA mode */
-			Or(BFFG, 0x01, BFFG)
-			Store(DerefOf(Index(UDTT, PDMM)), DSD0)
-		}
-		Else {
-			Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing,  DmaSpd0 */
-		}
-
-		If(And(PDCR, 0x02)) {	/* It's under UDMA mode */
-			Or(BFFG, 0x04, BFFG)
-			Store(DerefOf(Index(UDTT, PDSM)), DSD1)
-		}
-		Else {
-			Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing,  DmaSpd0 */
-		}
-
-		Return(OTBF) /* out buffer */
-	}				/* End Method(_GTM) */
-
-	Method(_STM, 3, NotSerialized)
-	{
-		NAME(INBF, Buffer(20) { /* in buffer */
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF,
-			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
-		})
-
-		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
-		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
-		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
-		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
-		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
-
-		Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
-		Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
-		Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
-		Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
-
-		Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
-		Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
-
-		If(And(BFFG, 0x01)) {	/* Drive 0 is under UDMA mode */
-			Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
-			Divide(Local0, 7, PDMM,)
-			Or(PDCR, 0x01, PDCR)
-		}
-		Else {
-			If(LNotEqual(DSD0, 0xFFFFFFFF)) {
-				Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
-				Store(DerefOf(Index(MDRT, Local0)), PMTM)
-			}
-		}
-
-		If(And(BFFG, 0x04)) {	/* Drive 1 is under UDMA mode */
-			Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
-			Divide(Local0, 7, PDSM,)
-			Or(PDCR, 0x02, PDCR)
-		}
-		Else {
-			If(LNotEqual(DSD1, 0xFFFFFFFF)) {
-				Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
-				Store(DerefOf(Index(MDRT, Local0)), PMTS)
-			}
-		}
-		/* Return(INBF) */
-	}		/*End Method(_STM) */
-	Device(MST)
-	{
-		Name(_ADR, 0)
-		Method(_GTF) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			Store(0xA0, CMDA)
-			Store(0xA0, CMDB)
-			Store(0xA0, CMDC)
-
-			Or(PPMM, 0x08, POMD)
-
-			If(And(PDCR, 0x01)) {
-				Or(PDMM, 0x40, DMMD)
-			}
-			Else {
-				Store(Match
-				      (MDTT, MLE, GTTM(PMTM),
-				       MTR, 0, 0), Local0)
-				If(LLess(Local0, 3)) {
-					Or(0x20, Local0, DMMD)
-				}
-			}
-			Return(CMBF)
-		}
-	}		/* End Device(MST) */
-
-	Device(SLAV)
-	{
-		Name(_ADR, 1)
-		Method(_GTF) {
-			Name(CMBF, Buffer(21) {
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
-				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
-			})
-			CreateByteField(CMBF, 1, POMD)
-			CreateByteField(CMBF, 8, DMMD)
-			CreateByteField(CMBF, 5, CMDA)
-			CreateByteField(CMBF, 12, CMDB)
-			CreateByteField(CMBF, 19, CMDC)
-
-			Store(0xB0, CMDA)
-			Store(0xB0, CMDB)
-			Store(0xB0, CMDC)
-
-			Or(PPSM, 0x08, POMD)
-
-			If(And(PDCR, 0x02)) {
-				Or(PDSM, 0x40, DMMD)
-			}
-			Else {
-				Store(Match
-				      (MDTT, MLE, GTTM(PMTS),
-				       MTR, 0, 0), Local0)
-				If(LLess(Local0, 3)) {
-					Or(0x20, Local0, DMMD)
-				}
-			}
-			Return(CMBF)
-		}
-	}			/* End Device(SLAV) */
-}
diff --git a/src/mainboard/asus/m4a785-m/acpi/routing.asl b/src/mainboard/asus/m4a785-m/acpi/routing.asl
deleted file mode 100644
index 072aa2117f..0000000000
--- a/src/mainboard/asus/m4a785-m/acpi/routing.asl
+++ /dev/null
@@ -1,297 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
-#include <arch/acpi.h>
-DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
-		)
-	{
-		#include "routing.asl"
-	}
-*/
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, INTC, 0 },
-		Package(){0x0002FFFF, 1, INTD, 0 },
-		Package(){0x0002FFFF, 2, INTA, 0 },
-		Package(){0x0002FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, INTA, 0 },
-		Package(){0x0004FFFF, 1, INTB, 0 },
-		Package(){0x0004FFFF, 2, INTC, 0 },
-		Package(){0x0004FFFF, 3, INTD, 0 },
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		/* Package(){0x0005FFFF, 0, INTB, 0 }, */
-		/* Package(){0x0005FFFF, 1, INTC, 0 }, */
-		/* Package(){0x0005FFFF, 2, INTD, 0 }, */
-		/* Package(){0x0005FFFF, 3, INTA, 0 }, */
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-		Package(){0x0006FFFF, 0, INTC, 0 },
-		Package(){0x0006FFFF, 1, INTD, 0 },
-		Package(){0x0006FFFF, 2, INTA, 0 },
-		Package(){0x0006FFFF, 3, INTB, 0 },
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-		Package(){0x0007FFFF, 0, INTD, 0 },
-		Package(){0x0007FFFF, 1, INTA, 0 },
-		Package(){0x0007FFFF, 2, INTB, 0 },
-		Package(){0x0007FFFF, 3, INTC, 0 },
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 1, INTA, 0 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
-		Package(){0x0012FFFF, 0, INTA, 0 },
-		Package(){0x0012FFFF, 1, INTB, 0 },
-		Package(){0x0013FFFF, 0, INTA, 0 },
-		Package(){0x0013FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTA, 0 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		/* Package(){0x0001FFFF, 0, 0, 18 }, */
-		/* Package(){0x0001FFFF, 1, 0, 19 }, */
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, 0, 18 },
-		/* Package(){0x0002FFFF, 1, 0, 19 }, */
-		/* Package(){0x0002FFFF, 2, 0, 16 }, */
-		/* Package(){0x0002FFFF, 3, 0, 17 }, */
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, 0, 19 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, 0, 16 },
-		/* Package(){0x0004FFFF, 1, 0, 17 }, */
-		/* Package(){0x0004FFFF, 2, 0, 18 }, */
-		/* Package(){0x0004FFFF, 3, 0, 19 }, */
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		/* Package(){0x0005FFFF, 0, 0, 17 }, */
-		/* Package(){0x0005FFFF, 1, 0, 18 }, */
-		/* Package(){0x0005FFFF, 2, 0, 19 }, */
-		/* Package(){0x0005FFFF, 3, 0, 16 }, */
-
-		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
-		/* Package(){0x0006FFFF, 0, 0, 18 }, */
-		/* Package(){0x0006FFFF, 1, 0, 19 }, */
-		/* Package(){0x0006FFFF, 2, 0, 16 }, */
-		/* Package(){0x0006FFFF, 3, 0, 17 }, */
-
-		/* Bus 0, Dev 7 - PCIe Bridge for network card */
-		/* Package(){0x0007FFFF, 0, 0, 19 }, */
-		/* Package(){0x0007FFFF, 1, 0, 16 }, */
-		/* Package(){0x0007FFFF, 2, 0, 17 }, */
-		/* Package(){0x0007FFFF, 3, 0, 18 }, */
-
-		/* Bus 0, Dev 9 - PCIe Bridge for network card */
-		Package(){0x0009FFFF, 0, 0, 17 },
-		/* Package(){0x0009FFFF, 1, 0, 16 }, */
-		/* Package(){0x0009FFFF, 2, 0, 17 }, */
-		/* Package(){0x0009FFFF, 3, 0, 18 }, */
-		/* Bus 0, Dev A - PCIe Bridge for network card */
-		Package(){0x000AFFFF, 0, 0, 18 },
-		/* Package(){0x000AFFFF, 1, 0, 16 }, */
-		/* Package(){0x000AFFFF, 2, 0, 17 }, */
-		/* Package(){0x000AFFFF, 3, 0, 18 }, */
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, 0, 22 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
-		Package(){0x0012FFFF, 0, 0, 16 },
-		Package(){0x0012FFFF, 1, 0, 17 },
-		Package(){0x0013FFFF, 0, 0, 18 },
-		Package(){0x0013FFFF, 1, 0, 19 },
-		Package(){0x0014FFFF, 0, 0, 16 },
-		/* Package(){0x00130004, 2, 0, 18 }, */
-		/* Package(){0x00130005, 3, 0, 19 }, */
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
-		Package(){0x0014FFFF, 0, 0, 16 },
-		Package(){0x0014FFFF, 1, 0, 17 },
-		Package(){0x0014FFFF, 2, 0, 18 },
-		Package(){0x0014FFFF, 3, 0, 19 },
-		/* Package(){0x00140004, 2, 0, 18 }, */
-		/* Package(){0x00140004, 3, 0, 19 }, */
-		/* Package(){0x00140005, 1, 0, 17 }, */
-		/* Package(){0x00140006, 1, 0, 17 }, */
-	})
-
-	Name(PR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, INTA, 0 },
-		Package(){0x0005FFFF, 1, INTB, 0 },
-		Package(){0x0005FFFF, 2, INTC, 0 },
-		Package(){0x0005FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, 0, 18 },
-		Package(){0x0005FFFF, 1, 0, 19 },
-		/* Package(){0x0005FFFF, 2, 0, 20 }, */
-		/* Package(){0x0005FFFF, 3, 0, 17 }, */
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-
-	Name(APS4, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-
-	Name(APS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-
-	Name(APS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-
-	Name(APS7, Package(){
-		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-	Name(PS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-
-	Name(APS9, Package(){
-		/* PCIe slot - Hooked to PCIe slot 9 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-	Name(PSa, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-
-	Name(APSa, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PCIB, Package(){
-		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
-		Package(){0x0005FFFF, 0, 0, 0x14 },
-		Package(){0x0005FFFF, 1, 0, 0x15 },
-		Package(){0x0005FFFF, 2, 0, 0x16 },
-		Package(){0x0005FFFF, 3, 0, 0x17 },
-		Package(){0x0006FFFF, 0, 0, 0x15 },
-		Package(){0x0006FFFF, 1, 0, 0x16 },
-		Package(){0x0006FFFF, 2, 0, 0x17 },
-		Package(){0x0006FFFF, 3, 0, 0x14 },
-		Package(){0x0007FFFF, 0, 0, 0x16 },
-		Package(){0x0007FFFF, 1, 0, 0x17 },
-		Package(){0x0007FFFF, 2, 0, 0x14 },
-		Package(){0x0007FFFF, 3, 0, 0x15 },
-	})
-}
diff --git a/src/mainboard/asus/m4a785-m/acpi/sata.asl b/src/mainboard/asus/m4a785-m/acpi/sata.asl
deleted file mode 100644
index cb9b221ba3..0000000000
--- a/src/mainboard/asus/m4a785-m/acpi/sata.asl
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-
-/*
-Scope (_SB) {
-	Device(PCI0) {
-		Device(SATA) {
-			Name(_ADR, 0x00110000)
-			#include "sata.asl"
-		}
-	}
-}
-*/
-
-Name(STTM, Buffer(20) {
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
-	0x1f, 0x00, 0x00, 0x00
-})
-
-/* Start by clearing the PhyRdyChg bits */
-Method(_INI) {
-	\_GPE._L1F()
-}
-
-Device(PMRY)
-{
-	Name(_ADR, 0)
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(PMST) {
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (LGreater(P0IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return  (0x00) /* sata is missing */
-			}
-		}
-	}/* end of PMST */
-
-	Device(PSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (LGreater(P1IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	}	/* end of PSLA */
-}   /* end of PMRY */
-
-
-Device(SEDY)
-{
-	Name(_ADR, 1)		/* IDE Scondary Channel */
-	Method(_GTM, 0x0, NotSerialized) {
-		Return(STTM)
-	}
-	Method(_STM, 0x3, NotSerialized) {}
-
-	Device(SMST)
-	{
-		Name(_ADR, 0)
-		Method(_STA,0) {
-			if (LGreater(P2IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SMST */
-
-	Device(SSLA)
-	{
-		Name(_ADR, 1)
-		Method(_STA,0) {
-			if (LGreater(P3IS,0)) {
-				return (0x0F) /* sata is visible */
-			}
-			else {
-				return (0x00) /* sata is missing */
-			}
-		}
-	} /* end of SSLA */
-}   /* end of SEDY */
-
-/* SATA Hot Plug Support */
-Scope(\_GPE) {
-	Method(_L1F,0x0,NotSerialized) {
-		if (\_SB.P0PR) {
-			if (LGreater(\_SB.P0IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P0PR)
-		}
-
-		if (\_SB.P1PR) {
-			if (LGreater(\_SB.P1IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P1PR)
-		}
-
-		if (\_SB.P2PR) {
-			if (LGreater(\_SB.P2IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P2PR)
-		}
-
-		if (\_SB.P3PR) {
-			if (LGreater(\_SB.P3IS,0)) {
-				sleep(32)
-			}
-			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
-			store(one, \_SB.P3PR)
-		}
-	}
-}
diff --git a/src/mainboard/asus/m4a785-m/acpi/usb.asl b/src/mainboard/asus/m4a785-m/acpi/usb.asl
deleted file mode 100644
index a3ccb97ff9..0000000000
--- a/src/mainboard/asus/m4a785-m/acpi/usb.asl
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-/*
-#include <arch/acpi.h>
-DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
-		)
-	{
-		#include "usb.asl"
-	}
-*/
-Method(UCOC, 0) {
-	Sleep(20)
-	Store(0x13,CMTI)
-	Store(0,GPSL)
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If(LLessEqual(UOM0,9)) {
-	Scope (\_GPE) {
-		Method (_L13) {
-			UCOC()
-			if(LEqual(GPB0,PLC0)) {
-				Not(PLC0,PLC0)
-				Store(PLC0, \_SB.PT0D)
-			}
-		}
-	}
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (LLessEqual(UOM1,9)) {
-	Scope (\_GPE) {
-		Method (_L14) {
-			UCOC()
-			if (LEqual(GPB1,PLC1)) {
-				Not(PLC1,PLC1)
-				Store(PLC1, \_SB.PT1D)
-			}
-		}
-	}
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (LLessEqual(UOM2,9)) {
-	Scope (\_GPE) {
-		Method (_L15) {
-			UCOC()
-			if (LEqual(GPB2,PLC2)) {
-				Not(PLC2,PLC2)
-				Store(PLC2, \_SB.PT2D)
-			}
-		}
-	}
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (LLessEqual(UOM3,9)) {
-	Scope (\_GPE) {
-		Method (_L16) {
-			UCOC()
-			if (LEqual(GPB3,PLC3)) {
-				Not(PLC3,PLC3)
-				Store(PLC3, \_SB.PT3D)
-			}
-		}
-	}
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (LLessEqual(UOM4,9)) {
-	Scope (\_GPE) {
-		Method (_L19) {
-			UCOC()
-			if (LEqual(GPB4,PLC4)) {
-				Not(PLC4,PLC4)
-				Store(PLC4, \_SB.PT4D)
-			}
-		}
-	}
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (LLessEqual(UOM5,9)) {
-	Scope (\_GPE) {
-		Method (_L1A) {
-			UCOC()
-			if (LEqual(GPB5,PLC5)) {
-				Not(PLC5,PLC5)
-				Store(PLC5, \_SB.PT5D)
-			}
-		}
-	}
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (LLessEqual(UOM6,9)) {
-	Scope (\_GPE) {
-		/* Method (_L1C) { */
-		Method (_L06) {
-			UCOC()
-			if (LEqual(GPB6,PLC6)) {
-				Not(PLC6,PLC6)
-				Store(PLC6, \_SB.PT6D)
-			}
-		}
-	}
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (LLessEqual(UOM7,9)) {
-	Scope (\_GPE) {
-		/* Method (_L1D) { */
-		Method (_L07) {
-			UCOC()
-			if (LEqual(GPB7,PLC7)) {
-				Not(PLC7,PLC7)
-				Store(PLC7, \_SB.PT7D)
-			}
-		}
-	}
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (LLessEqual(UOM8,9)) {
-	Scope (\_GPE) {
-		Method (_L17) {
-			if (LEqual(G8IS,PLC8)) {
-				Not(PLC8,PLC8)
-				Store(PLC8, \_SB.PT8D)
-			}
-		}
-	}
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (LLessEqual(UOM9,9)) {
-	Scope (\_GPE) {
-		Method (_L0E) {
-			if (LEqual(G9IS,0)) {
-			Store(1,\_SB.PT9D)
-			}
-		}
-	}
-}
diff --git a/src/mainboard/asus/m4a785-m/acpi_tables.c b/src/mainboard/asus/m4a785-m/acpi_tables.c
deleted file mode 100644
index cb263f90f2..0000000000
--- a/src/mainboard/asus/m4a785-m/acpi_tables.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <cpu/amd/amdfam10_sysconf.h>
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* create all subtables for processors */
-	current = acpi_create_madt_lapics(current);
-
-	/* Write SB700 IOAPIC, only one */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-                               CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
-
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 0, 2, 0);
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 9, 9, 0xF);
-	/* 0: mean bus 0--->ISA */
-	/* 0: PIC 0 */
-	/* 2: APIC 2 */
-	/* 5 mean: 0101 --> Edge-triggered, Active high */
-
-	/* create all subtables for processors */
-	/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
-	/* 1: LINT1 connect to NMI */
-
-	return current;
-}
diff --git a/src/mainboard/asus/m4a785-m/board_info.txt b/src/mainboard/asus/m4a785-m/board_info.txt
deleted file mode 100644
index c95f6f188b..0000000000
--- a/src/mainboard/asus/m4a785-m/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Category: desktop
-Board URL: http://www.asus.com/Motherboards/AMD_AM2Plus/M4A785M/
-ROM package: DIP8
-ROM protocol: SPI
-ROM socketed: y
-Flashrom support: y
-Release year: 2009
diff --git a/src/mainboard/asus/m4a785-m/cmos.layout b/src/mainboard/asus/m4a785-m/cmos.layout
deleted file mode 100644
index 6c3d3f6c9e..0000000000
--- a/src/mainboard/asus/m4a785-m/cmos.layout
+++ /dev/null
@@ -1,52 +0,0 @@
-entries
-
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#392          3       r       0        unused
-395          1       e       1        hw_scrubber
-396          1       e       1        interleave_chip_selects
-397          2       e       8        max_mem_clock
-399          1       e       2        multi_core
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-440          4       e       9        slow_cpu
-444          1       e       1        nmi
-445          1       e       1        gart
-456          1       e       1        ECC_memory
-728        256       h       0        user_data
-984         16       h       0        check_sum
-# Reserve the extended AMD configuration registers
-1000        24       r       0        amd_reserved
-
-
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     5     Notice
-6     6     Info
-6     7     Debug
-6     8     Spew
-8     0     400Mhz
-8     1     333Mhz
-8     2     266Mhz
-8     3     200Mhz
-9     0     off
-9     1     87.5%
-9     2     75.0%
-9     3     62.5%
-9     4     50.0%
-9     5     37.5%
-9     6     25.0%
-9     7     12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asus/m4a785-m/devicetree.cb b/src/mainboard/asus/m4a785-m/devicetree.cb
deleted file mode 100644
index 9dc937ccc7..0000000000
--- a/src/mainboard/asus/m4a785-m/devicetree.cb
+++ /dev/null
@@ -1,106 +0,0 @@
-chip northbridge/amd/amdfam10/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/socket_AM3  #L1 and DDR2
-			 device lapic 0 on end
-		end
-	end
-	device domain 0 on
-		subsystemid 0x1043 0x83a2 inherit
-		chip northbridge/amd/amdfam10
-			device pci 18.0 on #  northbridge
-				chip southbridge/amd/rs780
-					device pci 0.0 on end # HT	0x9600
-					device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
-					device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603
-					device pci 3.0 off end # PCIE P2P bridge	0x960b
-					device pci 4.0 off end # PCIE P2P bridge 0x9604
-					device pci 5.0 off end # PCIE P2P bridge 0x9605
-					device pci 6.0 off end # PCIE P2P bridge 0x9606
-					device pci 7.0 off end # PCIE P2P bridge 0x9607
-					device pci 8.0 off end # NB/SB Link P2P bridge
-					device pci 9.0 off end #
-					device pci a.0 on end # bridge to RTL8111/8168B PCI Express Gigabit Ethernet
-					register "gppsb_configuration" = "1"   # Configuration B
-					register "gpp_configuration" = "3"   # Configuration D default
-					register "port_enable" = "0x6fc"
-					register "gfx_dev2_dev3" = "1"
-					register "gfx_dual_slot" = "2"
-
-					register "gfx_lane_reversal" = "0"
-					register "gfx_tmds" = "0"
-					register "gfx_compliance" = "0"
-					register "gfx_reconfiguration" = "1"
-					register "gfx_link_width" = "0"
-				end
-				chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus
-					device pci 11.0 on end # SATA
-					device pci 12.0 on end # USB
-					device pci 12.1 on end # USB
-					device pci 12.2 on end # USB
-					device pci 13.0 on end # USB
-					device pci 13.1 on end # USB
-					device pci 13.2 on end # USB
-					device pci 14.0 on # SM
-						chip drivers/generic/generic #dimm 0-0-0
-							device i2c 50 on end
-						end
-						chip drivers/generic/generic #dimm 0-0-1
-							device i2c 51 on end
-						end
-						chip drivers/generic/generic #dimm 0-1-0
-							device i2c 52 on end
-						end
-						chip drivers/generic/generic #dimm 0-1-1
-							device i2c 53 on end
-						end
-					end # SM
-					device pci 14.1 on end # IDE    0x439c
-					device pci 14.2 on end # HDA    0x4383
-					device pci 14.3 on # LPC	0x439d
-						chip superio/ite/it8712f
-							device pnp 2e.0 off end #  Floppy
-							device pnp 2e.1 on #  Com1
-								io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.2 off #  Com2
-								io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							device pnp 2e.3 off #  Parallel Port
-								io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 2e.4 off end #  Environment Controller
-							device pnp 2e.5 on #  Keyboard
-								io 0x60 = 0x60
-								io 0x62 = 0x64
-								irq 0x70 = 1
-							end
-							device pnp 2e.6 on #  Mouse
-								irq 0x70 = 12
-							end
-							device pnp 2e.7 off #  GPIO, must be closed for unresolved reason.
-							end
-							device pnp 2e.8 off #  MIDI
-							end
-							device pnp 2e.9 off #  GAME
-							end
-							device pnp 2e.a off end #  CIR
-						end	#superio
-					end		#LPC
-					device pci 14.4 on end # PCI to PCI Bridge [1002:4384]
-					device pci 14.5 on end # USB 2
-					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-				end	#southbridge/amd/sb700
-			end #  device pci 18.0
-
-			device pci 18.0 on end
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-		end # chip northbridge
-	end #domain
-end # northbridge/amd/amdfam10/root_complex
diff --git a/src/mainboard/asus/m4a785-m/dsdt.asl b/src/mainboard/asus/m4a785-m/dsdt.asl
deleted file mode 100644
index eec3093b8e..0000000000
--- a/src/mainboard/asus/m4a785-m/dsdt.asl
+++ /dev/null
@@ -1,1718 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* DefinitionBlock Statement */
-#include <arch/acpi.h>
-DefinitionBlock (
-	"DSDT.AML",           /* Output filename */
-	"DSDT",                 /* Signature */
-	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	/* #include <arch/x86/acpi/debug.asl> */		/* Include global debug methods if needed */
-
-	/* Data to be patched by the BIOS during POST */
-	/* FIXME the patching is not done yet! */
-	/* Memory related values */
-	Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
-	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
-	Name(PBLN, 0x0)	/* Length of BIOS area */
-
-	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */
-	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
-
-	/* USB overcurrent mapping pins.   */
-	Name(UOM0, 0)
-	Name(UOM1, 2)
-	Name(UOM2, 0)
-	Name(UOM3, 7)
-	Name(UOM4, 2)
-	Name(UOM5, 2)
-	Name(UOM6, 6)
-	Name(UOM7, 2)
-	Name(UOM8, 6)
-	Name(UOM9, 6)
-
-	/* Some global data */
-	Name(OSVR, 3)		/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
-	Name(OSV, Ones)	/* Assume nothing */
-	Name(PMOD, One)	/* Assume APIC */
-
-	/*
-	 * Processor Object
-	 *
-	 */
-	Scope (\_PR) {		/* define processor scope */
-		Device (CPU0) {
-		Name (_HID, "ACPI0007")
-		Name (_UID, 0)
-			#include "acpi/cpstate.asl"
-		}
-		Device (CPU1) {
-		Name (_HID, "ACPI0007")
-		Name (_UID, 1)
-			#include "acpi/cpstate.asl"
-		}
-		Device (CPU2) {
-		Name (_HID, "ACPI0007")
-		Name (_UID, 2)
-			#include "acpi/cpstate.asl"
-		}
-		Device (CPU3) {
-		Name (_HID, "ACPI0007")
-		Name (_UID, 3)
-			#include "acpi/cpstate.asl"
-		}
-	} /* End _PR scope */
-
-	/* PIC IRQ mapping registers, C00h-C01h */
-	OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
-		Field(PRQM, ByteAcc, NoLock, Preserve) {
-		PRQI, 0x00000008,
-		PRQD, 0x00000008,  /* Offset: 1h */
-	}
-	IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
-		PINA, 0x00000008,	/* Index 0  */
-		PINB, 0x00000008,	/* Index 1 */
-		PINC, 0x00000008,	/* Index 2 */
-		PIND, 0x00000008,	/* Index 3 */
-		AINT, 0x00000008,	/* Index 4 */
-		SINT, 0x00000008,	/*  Index 5 */
-		, 0x00000008,	             /* Index 6 */
-		AAUD, 0x00000008,	/* Index 7 */
-		AMOD, 0x00000008,	/* Index 8 */
-		PINE, 0x00000008,	/* Index 9 */
-		PINF, 0x00000008,	/* Index A */
-		PING, 0x00000008,	/* Index B */
-		PINH, 0x00000008,	/* Index C */
-	}
-
-	/* PCI Error control register */
-	OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
-		Field(PERC, ByteAcc, NoLock, Preserve) {
-		SENS, 0x00000001,
-		PENS, 0x00000001,
-		SENE, 0x00000001,
-		PENE, 0x00000001,
-	}
-
-	/* Client Management index/data registers */
-	OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
-		Field(CMT, ByteAcc, NoLock, Preserve) {
-		CMTI,      8,
-		/* Client Management Data register */
-		G64E,   1,
-		G64O,      1,
-		G32O,      2,
-		,       2,
-		GPSL,     2,
-	}
-
-	/* GPM Port register */
-	OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
-		Field(GPT, ByteAcc, NoLock, Preserve) {
-		GPB0,1,
-		GPB1,1,
-		GPB2,1,
-		GPB3,1,
-		GPB4,1,
-		GPB5,1,
-		GPB6,1,
-		GPB7,1,
-	}
-
-	/* Flash ROM program enable register */
-	OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
-		Field(FRE, ByteAcc, NoLock, Preserve) {
-		,     0x00000006,
-		FLRE, 0x00000001,
-	}
-
-	/* PM2 index/data registers */
-	OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
-		Field(PM2R, ByteAcc, NoLock, Preserve) {
-		PM2I, 0x00000008,
-		PM2D, 0x00000008,
-	}
-
-	/* Power Management I/O registers */
-	OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
-		Field(PIOR, ByteAcc, NoLock, Preserve) {
-		PIOI, 0x00000008,
-		PIOD, 0x00000008,
-	}
-	IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
-		Offset(0x00),	/* MiscControl */
-		, 1,
-		T1EE, 1,
-		T2EE, 1,
-		Offset(0x01),	/* MiscStatus */
-		, 1,
-		T1E, 1,
-		T2E, 1,
-		Offset(0x04),	/* SmiWakeUpEventEnable3 */
-		, 7,
-		SSEN, 1,
-		Offset(0x07),	/* SmiWakeUpEventStatus3 */
-		, 7,
-		CSSM, 1,
-		Offset(0x10),	/* AcpiEnable */
-		, 6,
-		PWDE, 1,
-		Offset(0x1C),	/* ProgramIoEnable */
-		, 3,
-		MKME, 1,
-		IO3E, 1,
-		IO2E, 1,
-		IO1E, 1,
-		IO0E, 1,
-		Offset(0x1D),	/* IOMonitorStatus */
-		, 3,
-		MKMS, 1,
-		IO3S, 1,
-		IO2S, 1,
-		IO1S, 1,
-		IO0S,1,
-		Offset(0x20),	/* AcpiPmEvtBlk */
-		APEB, 16,
-		Offset(0x36),	/* GEvtLevelConfig */
-		, 6,
-		ELC6, 1,
-		ELC7, 1,
-		Offset(0x37),	/* GPMLevelConfig0 */
-		, 3,
-		PLC0, 1,
-		PLC1, 1,
-		PLC2, 1,
-		PLC3, 1,
-		PLC8, 1,
-		Offset(0x38),	/* GPMLevelConfig1 */
-		, 1,
-		 PLC4, 1,
-		 PLC5, 1,
-		, 1,
-		 PLC6, 1,
-		 PLC7, 1,
-		Offset(0x3B),	/* PMEStatus1 */
-		GP0S, 1,
-		GM4S, 1,
-		GM5S, 1,
-		APS, 1,
-		GM6S, 1,
-		GM7S, 1,
-		GP2S, 1,
-		STSS, 1,
-		Offset(0x55),	/* SoftPciRst */
-		SPRE, 1,
-		, 1,
-		, 1,
-		PNAT, 1,
-		PWMK, 1,
-		PWNS, 1,
-
-		/*	Offset(0x61), */	/*  Options_1 */
-		/*		,7,  */
-		/*		R617,1, */
-
-		Offset(0x65),	/* UsbPMControl */
-		, 4,
-		URRE, 1,
-		Offset(0x68),	/* MiscEnable68 */
-		, 3,
-		TMTE, 1,
-		, 1,
-		Offset(0x92),	/* GEVENTIN */
-		, 7,
-		E7IS, 1,
-		Offset(0x96),	/* GPM98IN */
-		G8IS, 1,
-		G9IS, 1,
-		Offset(0x9A),	/* EnhanceControl */
-		,7,
-		HPDE, 1,
-		Offset(0xA8),	/* PIO7654Enable */
-		IO4E, 1,
-		IO5E, 1,
-		IO6E, 1,
-		IO7E, 1,
-		Offset(0xA9),	/* PIO7654Status */
-		IO4S, 1,
-		IO5S, 1,
-		IO6S, 1,
-		IO7S, 1,
-	}
-
-	/* PM1 Event Block
-	* First word is PM1_Status, Second word is PM1_Enable
-	*/
-	OperationRegion(P1EB, SystemIO, APEB, 0x04)
-		Field(P1EB, ByteAcc, NoLock, Preserve) {
-		TMST, 1,
-		,    3,
-		BMST,    1,
-		GBST,   1,
-		Offset(0x01),
-		PBST, 1,
-		, 1,
-		RTST, 1,
-		, 3,
-		PWST, 1,
-		SPWS, 1,
-		Offset(0x02),
-		TMEN, 1,
-		, 4,
-		GBEN, 1,
-		Offset(0x03),
-		PBEN, 1,
-		, 1,
-		RTEN, 1,
-		, 3,
-		PWDA, 1,
-	}
-
-	Scope(\_SB) {
-		/* PCIe Configuration Space for 16 busses */
-		OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
-			Field(PCFG, ByteAcc, NoLock, Preserve) {
-			/* Byte offsets are computed using the following technique:
-			 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
-			 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
-			*/
-			Offset(0x00088024),	/* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
-			STB5, 32,
-			Offset(0x00098042),	/* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
-			PT0D, 1,
-			PT1D, 1,
-			PT2D, 1,
-			PT3D, 1,
-			PT4D, 1,
-			PT5D, 1,
-			PT6D, 1,
-			PT7D, 1,
-			PT8D, 1,
-			PT9D, 1,
-			Offset(0x000A0004),	/* Byte offset to SMBUS	register 4h - Bus 0, Device 20, Function 0 */
-			SBIE, 1,
-			SBME, 1,
-			Offset(0x000A0008),	/* Byte offset to SMBUS	register 8h - Bus 0, Device 20, Function 0 */
-			SBRI, 8,
-			Offset(0x000A0014),	/* Byte offset to SMBUS	register 14h - Bus 0, Device 20, Function 0 */
-			SBB1, 32,
-			Offset(0x000A0078),	/* Byte offset to SMBUS	register 78h - Bus 0, Device 20, Function 0 */
-			,14,
-			P92E, 1,		/* Port92 decode enable */
-		}
-
-		OperationRegion(SB5, SystemMemory, STB5, 0x1000)
-			Field(SB5, AnyAcc, NoLock, Preserve){
-			/* Port 0 */
-			Offset(0x120),		/* Port 0 Task file status */
-			P0ER, 1,
-			, 2,
-			P0DQ, 1,
-			, 3,
-			P0BY, 1,
-			Offset(0x128),		/* Port 0 Serial ATA status */
-			P0DD, 4,
-			, 4,
-			P0IS, 4,
-			Offset(0x12C),		/* Port 0 Serial ATA control */
-			P0DI, 4,
-			Offset(0x130),		/* Port 0 Serial ATA error */
-			, 16,
-			P0PR, 1,
-
-			/* Port 1 */
-			offset(0x1A0),		/* Port 1 Task file status */
-			P1ER, 1,
-			, 2,
-			P1DQ, 1,
-			, 3,
-			P1BY, 1,
-			Offset(0x1A8),		/* Port 1 Serial ATA status */
-			P1DD, 4,
-			, 4,
-			P1IS, 4,
-			Offset(0x1AC),		/* Port 1 Serial ATA control */
-			P1DI, 4,
-			Offset(0x1B0),		/* Port 1 Serial ATA error */
-			, 16,
-			P1PR, 1,
-
-			/* Port 2 */
-			Offset(0x220),		/* Port 2 Task file status */
-			P2ER, 1,
-			, 2,
-			P2DQ, 1,
-			, 3,
-			P2BY, 1,
-			Offset(0x228),		/* Port 2 Serial ATA status */
-			P2DD, 4,
-			, 4,
-			P2IS, 4,
-			Offset(0x22C),		/* Port 2 Serial ATA control */
-			P2DI, 4,
-			Offset(0x230),		/* Port 2 Serial ATA error */
-			, 16,
-			P2PR, 1,
-
-			/* Port 3 */
-			Offset(0x2A0),		/* Port 3 Task file status */
-			P3ER, 1,
-			, 2,
-			P3DQ, 1,
-			, 3,
-			P3BY, 1,
-			Offset(0x2A8),		/* Port 3 Serial ATA status */
-			P3DD, 4,
-			, 4,
-			P3IS, 4,
-			Offset(0x2AC),		/* Port 3 Serial ATA control */
-			P3DI, 4,
-			Offset(0x2B0),		/* Port 3 Serial ATA error */
-			, 16,
-			P3PR, 1,
-		}
-	}
-
-
-	#include "acpi/routing.asl"
-
-	Scope(\_SB) {
-
-		Method(OSFL, 0){
-
-			if(LNotEqual(OSVR, Ones)) {Return(OSVR)}	/* OS version was already detected */
-
-			if(CondRefOf(\_OSI))
-			{
-				Store(1, OSVR)                /* Assume some form of XP */
-				if (\_OSI("Windows 2006"))      /* Vista */
-				{
-					Store(2, OSVR)
-				}
-			} else {
-				If(WCMP(\_OS,"Linux")) {
-					Store(3, OSVR)            /* Linux */
-				} Else {
-					Store(4, OSVR)            /* Gotta be WinCE */
-				}
-			}
-			Return(OSVR)
-		}
-
-		Method(_PIC, 0x01, NotSerialized)
-		{
-			If (Arg0)
-			{
-				\_SB.CIRQ()
-			}
-			Store(Arg0, PMOD)
-		}
-		Method(CIRQ, 0x00, NotSerialized){
-			Store(0, PINA)
-			Store(0, PINB)
-			Store(0, PINC)
-			Store(0, PIND)
-			Store(0, PINE)
-			Store(0, PINF)
-			Store(0, PING)
-			Store(0, PINH)
-		}
-
-		Name(IRQB, ResourceTemplate(){
-			IRQ(Level,ActiveLow,Shared){15}
-		})
-
-		Name(IRQP, ResourceTemplate(){
-			IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
-		})
-
-		Name(PITF, ResourceTemplate(){
-			IRQ(Level,ActiveLow,Exclusive){9}
-		})
-
-		Device(INTA) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 1)
-
-			Method(_STA, 0) {
-				if (PINA) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTA._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKA\\_DIS\n") */
-				Store(0, PINA)
-			} /* End Method(_SB.INTA._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKA\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTA._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINA, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTA._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINA)
-			} /* End Method(_SB.INTA._SRS) */
-		} /* End Device(INTA) */
-
-		Device(INTB) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 2)
-
-			Method(_STA, 0) {
-				if (PINB) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTB._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKB\\_DIS\n") */
-				Store(0, PINB)
-			} /* End Method(_SB.INTB._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKB\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTB._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINB, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTB._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINB)
-			} /* End Method(_SB.INTB._SRS) */
-		} /* End Device(INTB)  */
-
-		Device(INTC) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 3)
-
-			Method(_STA, 0) {
-				if (PINC) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTC._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKC\\_DIS\n") */
-				Store(0, PINC)
-			} /* End Method(_SB.INTC._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKC\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTC._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINC, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTC._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINC)
-			} /* End Method(_SB.INTC._SRS) */
-		} /* End Device(INTC)  */
-
-		Device(INTD) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 4)
-
-			Method(_STA, 0) {
-				if (PIND) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTD._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKD\\_DIS\n") */
-				Store(0, PIND)
-			} /* End Method(_SB.INTD._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKD\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTD._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PIND, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTD._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PIND)
-			} /* End Method(_SB.INTD._SRS) */
-		} /* End Device(INTD)  */
-
-		Device(INTE) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 5)
-
-			Method(_STA, 0) {
-				if (PINE) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTE._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKE\\_DIS\n") */
-				Store(0, PINE)
-			} /* End Method(_SB.INTE._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKE\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTE._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINE, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTE._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINE)
-			} /* End Method(_SB.INTE._SRS) */
-		} /* End Device(INTE)  */
-
-		Device(INTF) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 6)
-
-			Method(_STA, 0) {
-				if (PINF) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTF._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKF\\_DIS\n") */
-				Store(0, PINF)
-			} /* End Method(_SB.INTF._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKF\\_PRS\n") */
-				Return(PITF)
-			} /* Method(_SB.INTF._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINF, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTF._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINF)
-			} /*  End Method(_SB.INTF._SRS) */
-		} /* End Device(INTF)  */
-
-		Device(INTG) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 7)
-
-			Method(_STA, 0) {
-				if (PING) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTG._STA)  */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKG\\_DIS\n") */
-				Store(0, PING)
-			} /* End Method(_SB.INTG._DIS)  */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKG\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTG._CRS)  */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PING, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTG._CRS)  */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PING)
-			} /* End Method(_SB.INTG._SRS)  */
-		} /* End Device(INTG)  */
-
-		Device(INTH) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 8)
-
-			Method(_STA, 0) {
-				if (PINH) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTH._STA)  */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKH\\_DIS\n") */
-				Store(0, PINH)
-			} /* End Method(_SB.INTH._DIS)  */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKH\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTH._CRS)  */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINH, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTH._CRS)  */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINH)
-			} /* End Method(_SB.INTH._SRS)  */
-		} /* End Device(INTH)   */
-
-	}   /* End Scope(_SB)  */
-
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Wake status package */
-	Name(WKST,Package(){Zero, Zero})
-
-	/*
-	* \_PTS - Prepare to Sleep method
-	*
-	*	Entry:
-	*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-	*
-	* Exit:
-	*		-none-
-	*
-	* The _PTS control method is executed at the beginning of the sleep process
-	* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-	* control method may be executed a relatively long time before entering the
-	* sleep state and the OS may abort the operation without notification to
-	* the ACPI driver.  This method cannot modify the configuration or power
-	* state of any device in the system.
-	*/
-	Method(\_PTS, 1) {
-		/* DBGO("\\_PTS\n") */
-		/* DBGO("From S0 to S") */
-		/* DBGO(Arg0) */
-		/* DBGO("\n") */
-
-		/* Don't allow PCIRST# to reset USB */
-		if (LEqual(Arg0,3)){
-			Store(0,URRE)
-		}
-
-		/* Clear sleep SMI status flag and enable sleep SMI trap. */
-		/*Store(One, CSSM)
-		Store(One, SSEN)*/
-
-		/* On older chips, clear PciExpWakeDisEn */
-		/*if (LLessEqual(\_SB.SBRI, 0x13)) {
-		*	Store(0,\_SB.PWDE)
-		*}
-		*/
-
-		/* Clear wake status structure. */
-		Store(0, Index(WKST,0))
-		Store(0, Index(WKST,1))
-		\_SB.PCI0.SIOS (Arg0)
-	} /* End Method(\_PTS) */
-
-	/*
-	*  The following method results in a "not a valid reserved NameSeg"
-	*  warning so I have commented it out for the duration.  It isn't
-	*  used, so it could be removed.
-	*
-	*
-	*	\_GTS OEM Going To Sleep method
-	*
-	*	Entry:
-	*		Arg0=The value of the sleeping state S1=1, S2=2
-	*
-	*	Exit:
-	*		-none-
-	*
-	*  Method(\_GTS, 1) {
-	*  DBGO("\\_GTS\n")
-	*  DBGO("From S0 to S")
-	*  DBGO(Arg0)
-	*  DBGO("\n")
-	*  }
-	*/
-
-	/*
-	*	\_BFS OEM Back From Sleep method
-	*
-	*	Entry:
-	*		Arg0=The value of the sleeping state S1=1, S2=2
-	*
-	*	Exit:
-	*		-none-
-	*/
-	Method(\_BFS, 1) {
-		/* DBGO("\\_BFS\n") */
-		/* DBGO("From S") */
-		/* DBGO(Arg0) */
-		/* DBGO(" to S0\n") */
-	}
-
-	/*
-	*  \_WAK System Wake method
-	*
-	*	Entry:
-	*		Arg0=The value of the sleeping state S1=1, S2=2
-	*
-	*	Exit:
-	*		Return package of 2 DWords
-	*		Dword 1 - Status
-	*			0x00000000	wake succeeded
-	*			0x00000001	Wake was signaled but failed due to lack of power
-	*			0x00000002	Wake was signaled but failed due to thermal condition
-	*		Dword 2 - Power Supply state
-	*			if non-zero the effective S-state the power supply entered
-	*/
-	Method(\_WAK, 1) {
-		/* DBGO("\\_WAK\n") */
-		/* DBGO("From S") */
-		/* DBGO(Arg0) */
-		/* DBGO(" to S0\n") */
-
-		/* Re-enable HPET */
-		Store(1,HPDE)
-
-		/* Restore PCIRST# so it resets USB */
-		if (LEqual(Arg0,3)){
-			Store(1,URRE)
-		}
-
-		/* Arbitrarily clear PciExpWakeStatus */
-		Store(PWST, Local1)
-		Store(Local1, PWST)
-
-		/* if (DeRefOf(Index(WKST,0))) {
-		*	Store(0, Index(WKST,1))
-		* } else {
-		*	Store(Arg0, Index(WKST,1))
-		* }
-		*/
-		\_SB.PCI0.SIOW ()
-		Return(WKST)
-	} /* End Method(\_WAK) */
-
-	Scope(\_GPE) {	/* Start Scope GPE */
-		/*  General event 0  */
-		/* Method(_L00) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
-
-		/*  General event 1  */
-		/* Method(_L01) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
-
-		/*  General event 2  */
-		/* Method(_L02) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
-
-		/*  General event 3  */
-		Method(_L03) {
-			/* DBGO("\\_GPE\\_L00\n") */
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/*  General event 4  */
-		/* Method(_L04) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
-
-		/*  General event 5  */
-		/* Method(_L05) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
-
-		/*  General event 6 - Used for GPM6, moved to USB.asl */
-		/* Method(_L06) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
-
-		/*  General event 7 - Used for GPM7, moved to USB.asl */
-		/* Method(_L07) {
-		*	DBGO("\\_GPE\\_L07\n")
-		* }
-		*/
-
-		/*  Legacy PM event  */
-		Method(_L08) {
-			/* DBGO("\\_GPE\\_L08\n") */
-		}
-
-		/*  Temp warning (TWarn) event  */
-		Method(_L09) {
-			/* DBGO("\\_GPE\\_L09\n") */
-			Notify (\_TZ.TZ00, 0x80)
-		}
-
-		/*  Reserved  */
-		/* Method(_L0A) {
-		*	DBGO("\\_GPE\\_L0A\n")
-		* }
-		*/
-
-		/*  USB controller PME#  */
-		Method(_L0B) {
-			/* DBGO("\\_GPE\\_L0B\n") */
-			Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/*  AC97 controller PME#  */
-		/* Method(_L0C) {
-		*	DBGO("\\_GPE\\_L0C\n")
-		* }
-		*/
-
-		/*  OtherTherm PME#  */
-		/* Method(_L0D) {
-		*	DBGO("\\_GPE\\_L0D\n")
-		* }
-		*/
-
-		/*  GPM9 SCI event - Moved to USB.asl */
-		/* Method(_L0E) {
-		*	DBGO("\\_GPE\\_L0E\n")
-		* }
-		*/
-
-		/*  PCIe HotPlug event  */
-		/* Method(_L0F) {
-		*	DBGO("\\_GPE\\_L0F\n")
-		* }
-		*/
-
-		/*  ExtEvent0 SCI event  */
-		Method(_L10) {
-			/* DBGO("\\_GPE\\_L10\n") */
-		}
-
-
-		/*  ExtEvent1 SCI event  */
-		Method(_L11) {
-			/* DBGO("\\_GPE\\_L11\n") */
-		}
-
-		/*  PCIe PME# event  */
-		/* Method(_L12) {
-		*	DBGO("\\_GPE\\_L12\n")
-		* }
-		*/
-
-		/*  GPM0 SCI event - Moved to USB.asl */
-		/* Method(_L13) {
-		*	DBGO("\\_GPE\\_L13\n")
-		* }
-		*/
-
-		/*  GPM1 SCI event - Moved to USB.asl */
-		/* Method(_L14) {
-		*	DBGO("\\_GPE\\_L14\n")
-		* }
-		*/
-
-		/*  GPM2 SCI event - Moved to USB.asl */
-		/* Method(_L15) {
-		*	DBGO("\\_GPE\\_L15\n")
-		* }
-		*/
-
-		/*  GPM3 SCI event - Moved to USB.asl */
-		/* Method(_L16) {
-		*	DBGO("\\_GPE\\_L16\n")
-		* }
-		*/
-
-		/*  GPM8 SCI event - Moved to USB.asl */
-		/* Method(_L17) {
-		*	DBGO("\\_GPE\\_L17\n")
-		* }
-		*/
-
-		/*  GPIO0 or GEvent8 event  */
-		Method(_L18) {
-			/* DBGO("\\_GPE\\_L18\n") */
-			Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/*  GPM4 SCI event - Moved to USB.asl */
-		/* Method(_L19) {
-		*	DBGO("\\_GPE\\_L19\n")
-		* }
-		*/
-
-		/*  GPM5 SCI event - Moved to USB.asl */
-		/* Method(_L1A) {
-		*	DBGO("\\_GPE\\_L1A\n")
-		* }
-		*/
-
-		/*  Azalia SCI event  */
-		Method(_L1B) {
-			/* DBGO("\\_GPE\\_L1B\n") */
-			Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-		}
-
-		/*  GPM6 SCI event - Reassigned to _L06 */
-		/* Method(_L1C) {
-		*	DBGO("\\_GPE\\_L1C\n")
-		* }
-		*/
-
-		/*  GPM7 SCI event - Reassigned to _L07 */
-		/* Method(_L1D) {
-		*	DBGO("\\_GPE\\_L1D\n")
-		* }
-		*/
-
-		/*  GPIO2 or GPIO66 SCI event  */
-		/* Method(_L1E) {
-		*	DBGO("\\_GPE\\_L1E\n")
-		* }
-		*/
-
-		/*  SATA SCI event - Moved to sata.asl */
-		/* Method(_L1F) {
-		*	 DBGO("\\_GPE\\_L1F\n")
-		* }
-		*/
-
-	}	/* End Scope GPE */
-
-	#include "acpi/usb.asl"
-
-	/* System Bus */
-	Scope(\_SB) { /* Start \_SB scope */
-		#include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
-
-		/*  _SB.PCI0 */
-		/* Note: Only need HID on Primary Bus */
-		Device(PCI0) {
-			External (TOM1)
-			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
-			Name(_HID, EISAID("PNP0A03"))
-			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
-			Method(_BBN, 0) { /* Bus number = 0 */
-				Return(0)
-			}
-			Method(_STA, 0) {
-				/* DBGO("\\_SB\\PCI0\\_STA\n") */
-				Return(0x0B)     /* Status is visible */
-			}
-
-			Method(_PRT,0) {
-				If(PMOD){ Return(APR0) }   /* APIC mode */
-				Return (PR0)                  /* PIC Mode */
-			} /* end _PRT */
-
-			/* Describe the Northbridge devices */
-			Device(AMRT) {
-				Name(_ADR, 0x00000000)
-			} /* end AMRT */
-
-			/* The internal GFX bridge */
-			Device(AGPB) {
-				Name(_ADR, 0x00010000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					Return (APR1)
-				}
-			}  /* end AGPB */
-
-			/* The external GFX bridge */
-			Device(PBR2) {
-				Name(_ADR, 0x00020000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APS2) }   /* APIC mode */
-					Return (PS2)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR2 */
-
-			/* Dev3 is also an external GFX bridge, not used in Herring */
-
-			Device(PBR4) {
-				Name(_ADR, 0x00040000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APS4) }   /* APIC mode */
-					Return (PS4)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR4 */
-
-			Device(PBR5) {
-				Name(_ADR, 0x00050000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APS5) }   /* APIC mode */
-					Return (PS5)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR5 */
-
-			Device(PBR6) {
-				Name(_ADR, 0x00060000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APS6) }   /* APIC mode */
-					Return (PS6)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR6 */
-
-			/* The onboard EtherNet chip */
-			Device(PBR7) {
-				Name(_ADR, 0x00070000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APS7) }   /* APIC mode */
-					Return (PS7)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR7 */
-
-			/* GPP */
-			Device(PBR9) {
-				Name(_ADR, 0x00090000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APS9) }   /* APIC mode */
-					Return (PS9)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR9 */
-
-			Device(PBRa) {
-				Name(_ADR, 0x000A0000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APSa) }   /* APIC mode */
-					Return (PSa)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBRa */
-
-
-			/* PCI slot 1, 2, 3 */
-			Device(PIBR) {
-				Name(_ADR, 0x00140004)
-				Name(_PRW, Package() {0x18, 4})
-
-				Method(_PRT, 0) {
-					Return (PCIB)
-				}
-			}
-
-			/* Describe the Southbridge devices */
-			Device(STCR) {
-				Name(_ADR, 0x00110000)
-				#include "acpi/sata.asl"
-			} /* end STCR */
-
-			Device(UOH1) {
-				Name(_ADR, 0x00130000)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH1 */
-
-			Device(UOH2) {
-				Name(_ADR, 0x00130001)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH2 */
-
-			Device(UOH3) {
-				Name(_ADR, 0x00130002)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH3 */
-
-			Device(UOH4) {
-				Name(_ADR, 0x00130003)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH4 */
-
-			Device(UOH5) {
-				Name(_ADR, 0x00130004)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH5 */
-
-			Device(UEH1) {
-				Name(_ADR, 0x00130005)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UEH1 */
-
-			Device(SBUS) {
-				Name(_ADR, 0x00140000)
-			} /* end SBUS */
-
-			/* Primary (and only) IDE channel */
-			Device(IDEC) {
-				Name(_ADR, 0x00140001)
-				#include "acpi/ide.asl"
-			} /* end IDEC */
-
-			Device(AZHD) {
-				Name(_ADR, 0x00140002)
-				OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
-					Field(AZPD, AnyAcc, NoLock, Preserve) {
-					offset (0x42),
-					NSDI, 1,
-					NSDO, 1,
-					NSEN, 1,
-					offset (0x44),
-					IPCR, 4,
-					offset (0x54),
-					PWST, 2,
-					, 6,
-					PMEB, 1,
-					, 6,
-					PMST, 1,
-					offset (0x62),
-					MMCR, 1,
-					offset (0x64),
-					MMLA, 32,
-					offset (0x68),
-					MMHA, 32,
-					offset (0x6C),
-					MMDT, 16,
-				}
-
-				Method(_INI) {
-					If(LEqual(OSVR,3)){   /* If we are running Linux */
-						Store(zero, NSEN)
-						Store(one, NSDO)
-						Store(one, NSDI)
-					}
-				}
-			} /* end AZHD */
-
-			Device(LIBR) {
-				Name(_ADR, 0x00140003)
-				/* Method(_INI) {
-				*	DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
-				} */ /* End Method(_SB.SBRDG._INI) */
-
-				/* Real Time Clock Device */
-				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
-					Name(_CRS, ResourceTemplate() {
-						IRQNoFlags(){8}
-						IO(Decode16,0x0070, 0x0070, 0, 2)
-						/* IO(Decode16,0x0070, 0x0070, 0, 4) */
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
-
-				Device(TMR) {	/* Timer */
-					Name(_HID,EISAID("PNP0100"))	/* System Timer */
-					Name(_CRS, ResourceTemplate() {
-						IRQNoFlags(){0}
-						IO(Decode16, 0x0040, 0x0040, 0, 4)
-						/* IO(Decode16, 0x0048, 0x0048, 0, 4) */
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
-
-				Device(SPKR) {	/* Speaker */
-					Name(_HID,EISAID("PNP0800"))	/* AT style speaker */
-					Name(_CRS, ResourceTemplate() {
-						IO(Decode16, 0x0061, 0x0061, 0, 1)
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
-
-				Device(PIC) {
-					Name(_HID,EISAID("PNP0000"))	/* AT Interrupt Controller */
-					Name(_CRS, ResourceTemplate() {
-						IRQNoFlags(){2}
-						IO(Decode16,0x0020, 0x0020, 0, 2)
-						IO(Decode16,0x00A0, 0x00A0, 0, 2)
-						/* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
-						/* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
-
-				Device(MAD) { /* 8257 DMA */
-					Name(_HID,EISAID("PNP0200"))	/* Hardware Device ID */
-					Name(_CRS, ResourceTemplate() {
-						DMA(Compatibility,BusMaster,Transfer8){4}
-						IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
-						IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
-						IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
-						IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
-						IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
-						IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
-					}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
-				} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
-
-				Device(COPR) {
-					Name(_HID,EISAID("PNP0C04"))	/* Math Coprocessor */
-					Name(_CRS, ResourceTemplate() {
-						IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
-						IRQNoFlags(){13}
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-
-				Device(HPTM) {
-					Name(_HID,EISAID("PNP0103"))
-					Name(CRS,ResourceTemplate()	{
-						Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT)	/* 1kb reserved space */
-					})
-					Method(_STA, 0) {
-						Return(0x0F) /* sata is visible */
-					}
-					Method(_CRS, 0)	{
-						CreateDwordField(CRS, ^HPT._BAS, HPBX)
-						Store(HPBA, HPBX)
-						Return(CRS)
-					}
-				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-			} /* end LIBR */
-
-			Device(HPBR) {
-				Name(_ADR, 0x00140004)
-			} /* end HostPciBr */
-
-			Device(ACAD) {
-				Name(_ADR, 0x00140005)
-			} /* end Ac97audio */
-
-			Device(ACMD) {
-				Name(_ADR, 0x00140006)
-			} /* end Ac97modem */
-
-			/* ITE8718 Support */
-			OperationRegion (IOID, SystemIO, 0x2E, 0x02)	/* sometimes it is 0x4E */
-				Field (IOID, ByteAcc, NoLock, Preserve)
-				{
-					SIOI,   8,    SIOD,   8		/* 0x2E and 0x2F */
-				}
-
-			IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
-			{
-					Offset (0x07),
-				LDN,	8,	/* Logical Device Number */
-					Offset (0x20),
-				CID1,	8,	/* Chip ID Byte 1, 0x87 */
-				CID2,	8,	/* Chip ID Byte 2, 0x12 */
-					Offset (0x30),
-				ACTR,	8,	/* Function activate */
-					Offset (0xF0),
-				APC0,	8,	/* APC/PME Event Enable Register */
-				APC1,	8,	/* APC/PME Status Register */
-				APC2,	8,	/* APC/PME Control Register 1 */
-				APC3,	8,	/* Environment Controller Special Configuration Register */
-				APC4,	8	/* APC/PME Control Register 2 */
-			}
-
-			/* Enter the 8718 MB PnP Mode */
-			Method (EPNP)
-			{
-				Store(0x87, SIOI)
-				Store(0x01, SIOI)
-				Store(0x55, SIOI)
-				Store(0x55, SIOI) /* 8718 magic number */
-			}
-			/* Exit the 8718 MB PnP Mode */
-			Method (XPNP)
-			{
-				Store (0x02, SIOI)
-				Store (0x02, SIOD)
-			}
-			/*
-			 * Keyboard PME is routed to SB700 Gevent3. We can wake
-			 * up the system by pressing the key.
-			 */
-			Method (SIOS, 1)
-			{
-				/* We only enable KBD PME for S5. */
-				If (LLess (Arg0, 0x05))
-				{
-					EPNP()
-					/* DBGO("8718F\n") */
-
-					Store (0x4, LDN)
-					Store (One, ACTR)  /* Enable EC */
-					/*
-					Store (0x4, LDN)
-					Store (0x04, APC4)
-					*/  /* falling edge. which mode? Not sure. */
-
-					Store (0x4, LDN)
-					Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
-					Store (0x4, LDN)
-					Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
-
-					XPNP()
-				}
-			}
-			Method (SIOW, 0)
-			{
-				EPNP()
-				Store (0x4, LDN)
-				Store (Zero, APC0) /* disable keyboard PME */
-				Store (0x4, LDN)
-				Store (0xFF, APC1) /* clear keyboard PME status */
-				XPNP()
-			}
-
-			Name(CRES, ResourceTemplate() {
-				IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)
-
-				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-					0x0000,			/* address granularity */
-					0x0000,			/* range minimum */
-					0x0CF7,			/* range maximum */
-					0x0000,			/* translation */
-					0x0CF8			/* length */
-				)
-
-				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-					0x0000,			/* address granularity */
-					0x0D00,			/* range minimum */
-					0xFFFF,			/* range maximum */
-					0x0000,			/* translation */
-					0xF300			/* length */
-				)
-
-				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
-				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM)	/* VGA memory space */
-				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
-				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
-
-				/* DRAM Memory from 1MB to TopMem */
-				Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)	/* 1MB to TopMem */
-
-				/* BIOS space just below 4GB */
-				DWORDMemory(
-					ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
-					0x00,			/* Granularity */
-					0x00000000,		/* Min */
-					0x00000000,		/* Max */
-					0x00000000,		/* Translation */
-					0x00000001,		/* Max-Min, RLEN */
-					,,
-					PCBM
-				)
-
-				/* DRAM memory from 4GB to TopMem2 */
-				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
-					0x00000000,		/* Granularity */
-					0x00000000,		/* Min */
-					0x00000000,		/* Max */
-					0x00000000,		/* Translation */
-					0x00000001,		/* Max-Min, RLEN */
-					,,
-					DMHI
-				)
-
-				/* BIOS space just below 16EB */
-				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
-					0x00000000,		/* Granularity */
-					0x00000000,		/* Min */
-					0x00000000,		/* Max */
-					0x00000000,		/* Translation */
-					0x00000001,		/* Max-Min, RLEN */
-					,,
-					PEBM
-				)
-
-			}) /* End Name(_SB.PCI0.CRES) */
-
-			Method(_CRS, 0) {
-				/* DBGO("\\_SB\\PCI0\\_CRS\n") */
-
-				CreateDWordField(CRES, ^EMM1._BAS, EM1B)
-				CreateDWordField(CRES, ^EMM1._LEN, EM1L)
-				CreateDWordField(CRES, ^DMLO._BAS, DMLB)
-				CreateDWordField(CRES, ^DMLO._LEN, DMLL)
-				CreateDWordField(CRES, ^PCBM._MIN, PBMB)
-				CreateDWordField(CRES, ^PCBM._LEN, PBML)
-
-				CreateQWordField(CRES, ^DMHI._MIN, DMHB)
-				CreateQWordField(CRES, ^DMHI._LEN, DMHL)
-				CreateQWordField(CRES, ^PEBM._MIN, EBMB)
-				CreateQWordField(CRES, ^PEBM._LEN, EBML)
-
-				If(LGreater(LOMH, 0xC0000)){
-					Store(0xC0000, EM1B)	/* Hole above C0000 and below E0000 */
-					Subtract(LOMH, 0xC0000, EM1L)	/* subtract start, assumes allocation from C0000 going up */
-				}
-
-				/* Set size of memory from 1MB to TopMem */
-				Subtract(TOM1, 0x100000, DMLL)
-
-				/*
-				* If(LNotEqual(TOM2, 0x00000000)){
-				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
-				*	ShiftLeft(TOM2, 20, Local0)
-				*	Subtract(Local0, 0x100000000, DMHL)
-				* }
-				*/
-
-				/* If there is no memory above 4GB, put the BIOS just below 4GB */
-				If(LEqual(TOM2, 0x00000000)){
-					Store(PBAD,PBMB)			/* Reserve the "BIOS" space */
-					Store(PBLN,PBML)
-				}
-				Else {  /* Otherwise, put the BIOS just below 16EB */
-					ShiftLeft(PBAD,16,EBMB)		/* Reserve the "BIOS" space */
-					Store(PBLN,EBML)
-				}
-
-				Return(CRES) /* note to change the Name buffer */
-			}  /* end of Method(_SB.PCI0._CRS) */
-
-			/*
-			*
-			*               FIRST METHOD CALLED UPON BOOT
-			*
-			*  1. If debugging, print current OS and ACPI interpreter.
-			*  2. Get PCI Interrupt routing from ACPI VSM, this
-			*     value is based on user choice in BIOS setup.
-			*/
-			Method(_INI, 0) {
-				/* DBGO("\\_SB\\_INI\n") */
-				/* DBGO("   DSDT.ASL code from ") */
-				/* DBGO(__DATE__) */
-				/* DBGO(" ") */
-				/* DBGO(__TIME__) */
-				/* DBGO("\n   Sleep states supported: ") */
-				/* DBGO("\n") */
-				/* DBGO("   \\_OS=") */
-				/* DBGO(\_OS) */
-				/* DBGO("\n   \\_REV=") */
-				/* DBGO(\_REV) */
-				/* DBGO("\n") */
-
-				/* Determine the OS we're running on */
-				OSFL()
-
-				/* On older chips, clear PciExpWakeDisEn */
-				/*if (LLessEqual(\SBRI, 0x13)) {
-				*	Store(0,\PWDE)
-				* }
-				*/
-			} /* End Method(_SB._INI) */
-		} /* End Device(PCI0)  */
-
-		Device(PWRB) {	/* Start Power button device */
-			Name(_HID, EISAID("PNP0C0C"))
-			Name(_UID, 0xAA)
-			Name(_PRW, Package () {3, 0x04})	/* wake from S1-S4 */
-			Name(_STA, 0x0B) /* sata is invisible */
-		}
-	} /* End \_SB scope */
-
-	Scope(\_SI) {
-		Method(_SST, 1) {
-			/* DBGO("\\_SI\\_SST\n") */
-			/* DBGO("   New Indicator state: ") */
-			/* DBGO(Arg0) */
-			/* DBGO("\n") */
-		}
-	} /* End Scope SI */
-
-	#include <southbridge/amd/cimx/sb800/acpi/smbus.asl>
-
-	/* THERMAL */
-	Scope(\_TZ) {
-		Name (KELV, 2732)
-		Name (THOT, 800)
-		Name (TCRT, 850)
-
-		ThermalZone(TZ00) {
-			Method(_AC0,0) {	/* Active Cooling 0 (0=highest fan speed) */
-				/* DBGO("\\_TZ\\TZ00\\_AC0\n") */
-				Return(Add(0, 2730))
-			}
-			Method(_AL0,0) {	/* Returns package of cooling device to turn on */
-				/* DBGO("\\_TZ\\TZ00\\_AL0\n") */
-				Return(Package() {\_TZ.TZ00.FAN0})
-			}
-			Device (FAN0) {
-				Name(_HID, EISAID("PNP0C0B"))
-				Name(_PR0, Package() {PFN0})
-			}
-
-			PowerResource(PFN0,0,0) {
-				Method(_STA) {
-					Store(0xF,Local0)
-					Return(Local0)
-				}
-				Method(_ON) {
-					/* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
-				}
-				Method(_OFF) {
-					/* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
-				}
-			}
-
-			Method(_HOT,0) {	/* return hot temp in tenths degree Kelvin */
-				/* DBGO("\\_TZ\\TZ00\\_HOT\n") */
-				Return (Add (THOT, KELV))
-			}
-			Method(_CRT,0) {	/* return critical temp in tenths degree Kelvin */
-				/* DBGO("\\_TZ\\TZ00\\_CRT\n") */
-				Return (Add (TCRT, KELV))
-			}
-			Method(_TMP,0) {	/* return current temp of this zone */
-				Store (SMBR (0x07, 0x4C,, 0x00), Local0)
-				If (LGreater (Local0, 0x10)) {
-					Store (Local0, Local1)
-				}
-				Else {
-					Add (Local0, THOT, Local0)
-					Return (Add (400, KELV))
-				}
-
-				Store (SMBR (0x07, 0x4C, 0x01), Local0)
-				/* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
-				/* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
-				If (LGreater (Local0, 0x10)) {
-					If (LGreater (Local0, Local1)) {
-						Store (Local0, Local1)
-					}
-
-					Multiply (Local1, 10, Local1)
-					Return (Add (Local1, KELV))
-				}
-				Else {
-					Add (Local0, THOT, Local0)
-					Return (Add (400 , KELV))
-				}
-			} /* end of _TMP */
-		} /* end of TZ00 */
-	}
-}
-/* End of ASL file */
diff --git a/src/mainboard/asus/m4a785-m/get_bus_conf.c b/src/mainboard/asus/m4a785-m/get_bus_conf.c
deleted file mode 100644
index ee2a6caeb9..0000000000
--- a/src/mainboard/asus/m4a785-m/get_bus_conf.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/pci.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdfam10_sysconf.h>
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u32 apicid_sb700;
-
-void get_bus_conf(void)
-{
-	u32 apicid_base;
-
-	get_default_pci1234(1);
-
-	sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
-
-	pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
-
-	/* I/O APICs:   APIC ID Version State   Address */
-	if (CONFIG(LOGICAL_CPUS))
-		apicid_base = get_apicid_base(1);
-	else
-		apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
-	apicid_sb700 = apicid_base + 0;
-}
diff --git a/src/mainboard/asus/m4a785-m/irq_tables.c b/src/mainboard/asus/m4a785-m/irq_tables.c
deleted file mode 100644
index 9e114a312b..0000000000
--- a/src/mainboard/asus/m4a785-m/irq_tables.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Juhana Helovuo <juhe@iki.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,		/* u32 signature */
-	PIRQ_VERSION,		/* u16 version */
-	32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
-	0x00,			/* Interrupt router bus */
-	(0x14 << 3) | 0x3,	/* Interrupt router dev */
-	0,			/* IRQs devoted exclusively to PCI usage */
-	0x1002,			/* Vendor */
-	0x439d,			/* Device */
-	0,			/* Miniport */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x8,			/* Checksum (has to be set to some value that
-				 * would give 0 after the sum of all bytes
-				 * for this structure (including checksum).
-				 */
-	{
-		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
-		{0x01, (0x05 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
-		{0x00, (0x02 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
-		{0x00, (0x03 << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0},
-		{0x00, (0x04 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
-		{0x00, (0x05 << 3) | 0x0, {{0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}}, 0x0, 0x0},
-		{0x00, (0x06 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
-		{0x00, (0x07 << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0},
-		{0x00, (0x09 << 3) | 0x0, {{0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}}, 0x0, 0x0},
-		{0x00, (0x0a << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
-		{0x02, (0x00 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0xa, 0x0},
-		{0x00, (0x0b << 3) | 0x0, {{0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}}, 0x0, 0x0},
-		{0x00, (0x0c << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
-		{0x00, (0x14 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
-		{0x00, (0x12 << 3) | 0x0, {{0x01, 0xdc90}, {0x02, 0xdc90}, {0x03, 0xdc90}, {0x04, 0xdc90}}, 0x0, 0x0},
-		{0x00, (0x13 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
-		{0x00, (0x11 << 3) | 0x0, {{0x0c, 0xdc90}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-		{0x0a, (0x00 << 3) | 0x0, {{0x03, 0xdc90}, {0x04, 0xdc90}, {0x01, 0xdc90}, {0x02, 0xdc90}}, 0x0, 0x0},
-		{0x03, (0x05 << 3) | 0x0, {{0x0a, 0xdc90}, {0x0b, 0xdc90}, {0x0c, 0xdc90}, {0x0d, 0xdc90}}, 0xc, 0x0},
-		{0x03, (0x06 << 3) | 0x0, {{0x0b, 0xdc90}, {0x0c, 0xdc90}, {0x0d, 0xdc90}, {0x0a, 0xdc90}}, 0xd, 0x0},
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c
deleted file mode 100644
index aa6b920db2..0000000000
--- a/src/mainboard/asus/m4a785-m/mainboard.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
-#include <southbridge/amd/sb700/smbus.h>
-#include <southbridge/amd/rs780/rs780.h>
-
-#define ADT7461_ADDRESS 0x4C
-#define ARA_ADDRESS     0x0C /* Alert Response Address */
-
-#define ADT7461_read_byte(address) \
-	do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
-#define ARA_read_byte(address) \
-	do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
-#define ADT7461_write_byte(address, val) \
-	do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
-
-void set_pcie_dereset(void)
-{
-	u8 byte;
-	u16 word;
-	struct device *sm_dev;
-	/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
-	/* set 0 to bit2 :disable GPM8 as AZ_RST output */
-	byte = pm_ioread(0x8d);
-	byte &= ~((1 << 1) | (1 << 2));
-	pm_iowrite(0x8d, byte);
-
-	/* set the GPM8 and GPM9 output enable and the value to 1 */
-	byte = pm_ioread(0x94);
-	byte &= ~((1 << 2) | (1 << 3));
-	byte |=  ((1 << 0) | (1 << 1));
-	pm_iowrite(0x94, byte);
-
-	/* set the GPIO65 output enable and the value is 1 */
-	sm_dev = pcidev_on_root(0x14, 0);
-	word = pci_read_config16(sm_dev, 0x7e);
-	word |= (1 << 0);
-	word &= ~(1 << 4);
-	pci_write_config16(sm_dev, 0x7e, word);
-}
-
-void set_pcie_reset(void)
-{
-	u8 byte;
-	u16 word;
-	struct device *sm_dev;
-
-	/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
-	/* set 0 to bit2 :disable GPM8 as AZ_RST output */
-	byte = pm_ioread(0x8d);
-	byte &= ~((1 << 1) | (1 << 2));
-	pm_iowrite(0x8d, byte);
-
-	/* set the GPM8 and GPM9 output enable and the value to 0 */
-	byte = pm_ioread(0x94);
-	byte &= ~((1 << 2) | (1 << 3));
-	byte &= ~((1 << 0) | (1 << 1));
-	pm_iowrite(0x94, byte);
-
-	/* set the GPIO65 output enable and the value is 0 */
-	sm_dev = pcidev_on_root(0x14, 0);
-	word = pci_read_config16(sm_dev, 0x7e);
-	word &= ~(1 << 0);
-	word &= ~(1 << 4);
-	pci_write_config16(sm_dev, 0x7e, word);
-}
-
-/*
- * justify the dev3 is exist or not
- * NOTE: This just copied from AMD Tilapia code.
- * It is completely unknown it it will work at all for ASUS M4A785-M.
- */
-int is_dev3_present(void)
-{
-	u16 word;
-	struct device *sm_dev;
-
-	/* access the smbus extended register */
-	sm_dev = pcidev_on_root(0x14, 0);
-
-	/* put the GPIO68 output to tristate */
-	word = pci_read_config16(sm_dev, 0x7e);
-	word |= 1 << 6;
-	pci_write_config16(sm_dev, 0x7e,word);
-
-	/* read the GPIO68 input status */
-	word = pci_read_config16(sm_dev, 0x7e);
-
-	return !(word & (1 << 10));
-}
-
-/*
- * set thermal config
- */
-static void set_thermal_config(void)
-{
-	u8 byte;
-	u16 word;
-	struct device *sm_dev;
-
-	/* set ADT 7461 */
-	ADT7461_write_byte(0x0B, 0x50);	/* Local Temperature Hight limit */
-	ADT7461_write_byte(0x0C, 0x00);	/* Local Temperature Low limit */
-	ADT7461_write_byte(0x0D, 0x50);	/* External Temperature Hight limit  High Byte */
-	ADT7461_write_byte(0x0E, 0x00);	/* External Temperature Low limit High Byte */
-
-	ADT7461_write_byte(0x19, 0x55);	/* External THERM limit */
-	ADT7461_write_byte(0x20, 0x55);	/* Local THERM limit */
-
-	byte = ADT7461_read_byte(0x02);	/* read status register to clear it */
-	ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
-	printk(BIOS_INFO, "Init adt7461 end, status 0x02 %02x\n", byte);
-
-	/* sb700 settings for thermal config */
-	/* set SB700 GPIO 64 to GPIO with pull-up */
-	byte = pm2_ioread(0x42);
-	byte &= 0x3f;
-	pm2_iowrite(0x42, byte);
-
-	/* set GPIO 64 to input */
-	sm_dev = pcidev_on_root(0x14, 0);
-	word = pci_read_config16(sm_dev, 0x56);
-	word |= 1 << 7;
-	pci_write_config16(sm_dev, 0x56, word);
-
-	/* set GPIO 64 internal pull-up */
-	byte = pm2_ioread(0xf0);
-	byte &= 0xee;
-	pm2_iowrite(0xf0, byte);
-
-	/* set Talert to be active low */
-	byte = pm_ioread(0x67);
-	byte &= ~(1 << 5);
-	pm_iowrite(0x67, byte);
-
-	/* set Talert to generate ACPI event */
-	byte = pm_ioread(0x3c);
-	byte &= 0xf3;
-	pm_iowrite(0x3c, byte);
-
-	/* THERMTRIP pin */
-	/* byte = pm_ioread(0x68);
-	 * byte |= 1 << 3;
-	 * pm_iowrite(0x68, byte);
-	 *
-	 * byte = pm_ioread(0x55);
-	 * byte |= 1 << 0;
-	 * pm_iowrite(0x55, byte);
-	 *
-	 * byte = pm_ioread(0x67);
-	 * byte &= ~(1 << 6);
-	 * pm_iowrite(0x67, byte);
-	 */
-}
-
-/*************************************************
-* enable the dedicated function in this board.
-* This function called early than rs780_enable.
-*************************************************/
-static void mainboard_enable(struct device *dev)
-{
-	printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev);
-
-	set_pcie_dereset();
-	/* get_ide_dma66(); */
-	set_thermal_config();
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/asus/m4a785-m/mptable.c b/src/mainboard/asus/m4a785-m/mptable.c
deleted file mode 100644
index b04a315bb1..0000000000
--- a/src/mainboard/asus/m4a785-m/mptable.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <stdint.h>
-#include <cpu/amd/amdfam10_sysconf.h>
-
-extern u32 apicid_sb700;
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	int bus_isa;
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-	smp_write_processors(mc);
-
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-	/* I/O APICs:   APIC ID Version State   Address */
-	{
-		struct device *dev;
-		u32 dword;
-		u8 byte;
-
-		dev =
-		    dev_find_slot(pirq_router_bus,
-				  PCI_DEVFN(0x14, 0));
-		if (dev) {
-			dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
-			smp_write_ioapic(mc, apicid_sb700,
-					 0x11,(void *) dword);
-
-			/* Initialize interrupt mapping */
-			/* aza */
-			byte = pci_read_config8(dev, 0x63);
-			byte &= 0xf8;
-			byte |= 0;	/* 0: INTA, ...., 7: INTH */
-			pci_write_config8(dev, 0x63, byte);
-
-			/* SATA */
-			dword = pci_read_config32(dev, 0xac);
-			dword &= ~(7 << 26);
-			dword |= 6 << 26;	/* 0: INTA, ...., 7: INTH */
-			/* dword |= 1 << 22; PIC and APIC co exists */
-			pci_write_config32(dev, 0xac, dword);
-
-			/*
-			 * 00:12.0: PROG SATA : INT F
-			 * 00:13.0: INTA USB_0
-			 * 00:13.1: INTB USB_1
-			 * 00:13.2: INTC USB_2
-			 * 00:13.3: INTD USB_3
-			 * 00:13.4: INTC USB_4
-			 * 00:13.5: INTD USB2
-			 * 00:14.1: INTA IDE
-			 * 00:14.2: Prog HDA : INT E
-			 * 00:14.5: INTB ACI
-			 * 00:14.6: INTB MCI
-			 */
-		}
-	}
-
-	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
-	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
-	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
-
-	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
-	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);
-	return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asus/m4a785-m/resourcemap.c b/src/mainboard/asus/m4a785-m/resourcemap.c
deleted file mode 100644
index 80d2d9d05c..0000000000
--- a/src/mainboard/asus/m4a785-m/resourcemap.c
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-
-#include <commonlib/helpers.h>
-#include <northbridge/amd/amdfam10/amdfam10.h>
-
-void setup_mb_resource_map(void)
-{
-	static const unsigned int register_values[] = {
-		/* Careful set limit registers before base registers which contain the enables */
-		/* DRAM Limit i Registers
-		 * F1:0x44 i = 0
-		 * F1:0x4C i = 1
-		 * F1:0x54 i = 2
-		 * F1:0x5C i = 3
-		 * F1:0x64 i = 4
-		 * F1:0x6C i = 5
-		 * F1:0x74 i = 6
-		 * F1:0x7C i = 7
-		 * [ 2: 0] Destination Node ID
-		 *	   000 = Node 0
-		 *	   001 = Node 1
-		 *	   010 = Node 2
-		 *	   011 = Node 3
-		 *	   100 = Node 4
-		 *	   101 = Node 5
-		 *	   110 = Node 6
-		 *	   111 = Node 7
-		 * [ 7: 3] Reserved
-		 * [10: 8] Interleave select
-		 *	   specifies the values of A[14:12] to use with interleave enable.
-		 * [15:11] Reserved
-		 * [31:16] DRAM Limit Address i Bits 39-24
-		 *	   This field defines the upper address bits of a 40 bit  address
-		 *	   that define the end of the DRAM region.
-		 */
-//		ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
-		ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
-		ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
-		ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
-		ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
-		ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
-		ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
-		ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
-		/* DRAM Base i Registers
-		 * F1:0x40 i = 0
-		 * F1:0x48 i = 1
-		 * F1:0x50 i = 2
-		 * F1:0x58 i = 3
-		 * F1:0x60 i = 4
-		 * F1:0x68 i = 5
-		 * F1:0x70 i = 6
-		 * F1:0x78 i = 7
-		 * [ 0: 0] Read Enable
-		 *	   0 = Reads Disabled
-		 *	   1 = Reads Enabled
-		 * [ 1: 1] Write Enable
-		 *	   0 = Writes Disabled
-		 *	   1 = Writes Enabled
-		 * [ 7: 2] Reserved
-		 * [10: 8] Interleave Enable
-		 *	   000 = No interleave
-		 *	   001 = Interleave on A[12] (2 nodes)
-		 *	   010 = reserved
-		 *	   011 = Interleave on A[12] and A[14] (4 nodes)
-		 *	   100 = reserved
-		 *	   101 = reserved
-		 *	   110 = reserved
-		 *	   111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
-		 * [15:11] Reserved
-		 * [13:16] DRAM Base Address i Bits 39-24
-		 *	   This field defines the upper address bits of a 40-bit address
-		 *	   that define the start of the DRAM region.
-		 */
-//		ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
-		ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
-		ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
-		ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
-		ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
-		ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
-		ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
-		ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
-
-		/* Memory-Mapped I/O Limit i Registers
-		 * F1:0x84 i = 0
-		 * F1:0x8C i = 1
-		 * F1:0x94 i = 2
-		 * F1:0x9C i = 3
-		 * F1:0xA4 i = 4
-		 * F1:0xAC i = 5
-		 * F1:0xB4 i = 6
-		 * F1:0xBC i = 7
-		 * [ 2: 0] Destination Node ID
-		 *	   000 = Node 0
-		 *	   001 = Node 1
-		 *	   010 = Node 2
-		 *	   011 = Node 3
-		 *	   100 = Node 4
-		 *	   101 = Node 5
-		 *	   110 = Node 6
-		 *	   111 = Node 7
-		 * [ 3: 3] Reserved
-		 * [ 5: 4] Destination Link ID
-		 *	   00 = Link 0
-		 *	   01 = Link 1
-		 *	   10 = Link 2
-		 *	   11 = Reserved
-		 * [ 6: 6] Reserved
-		 * [ 7: 7] Non-Posted
-		 *	   0 = CPU writes may be posted
-		 *	   1 = CPU writes must be non-posted
-		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	   This field defines the upp address bits of a 40-bit address that
-		 *	   defines the end of a memory-mapped I/O region n
-		 */
-		ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
-		ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
-		ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
-		ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
-		ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
-		ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
-		ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
-//		ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
-
-		/* Memory-Mapped I/O Base i Registers
-		 * F1:0x80 i = 0
-		 * F1:0x88 i = 1
-		 * F1:0x90 i = 2
-		 * F1:0x98 i = 3
-		 * F1:0xA0 i = 4
-		 * F1:0xA8 i = 5
-		 * F1:0xB0 i = 6
-		 * F1:0xB8 i = 7
-		 * [ 0: 0] Read Enable
-		 *	   0 = Reads disabled
-		 *	   1 = Reads Enabled
-		 * [ 1: 1] Write Enable
-		 *	   0 = Writes disabled
-		 *	   1 = Writes Enabled
-		 * [ 2: 2] Cpu Disable
-		 *	   0 = Cpu can use this I/O range
-		 *	   1 = Cpu requests do not use this I/O range
-		 * [ 3: 3] Lock
-		 *	   0 = base/limit registers i are read/write
-		 *	   1 = base/limit registers i are read-only
-		 * [ 7: 4] Reserved
-		 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
-		 *	   This field defines the upper address bits of a 40bit address
-		 *	   that defines the start of memory-mapped I/O region i
-		 */
-		ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
-		ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
-		ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
-		ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
-		ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
-		ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
-		ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
-//		ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
-
-		/* PCI I/O Limit i Registers
-		 * F1:0xC4 i = 0
-		 * F1:0xCC i = 1
-		 * F1:0xD4 i = 2
-		 * F1:0xDC i = 3
-		 * [ 2: 0] Destination Node ID
-		 *	   000 = Node 0
-		 *	   001 = Node 1
-		 *	   010 = Node 2
-		 *	   011 = Node 3
-		 *	   100 = Node 4
-		 *	   101 = Node 5
-		 *	   110 = Node 6
-		 *	   111 = Node 7
-		 * [ 3: 3] Reserved
-		 * [ 5: 4] Destination Link ID
-		 *	   00 = Link 0
-		 *	   01 = Link 1
-		 *	   10 = Link 2
-		 *	   11 = reserved
-		 * [11: 6] Reserved
-		 * [24:12] PCI I/O Limit Address i
-		 *	   This field defines the end of PCI I/O region n
-		 * [31:25] Reserved
-		 */
-//		ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000,
-		ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000,
-		ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
-		ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
-
-		/* PCI I/O Base i Registers
-		 * F1:0xC0 i = 0
-		 * F1:0xC8 i = 1
-		 * F1:0xD0 i = 2
-		 * F1:0xD8 i = 3
-		 * [ 0: 0] Read Enable
-		 *	   0 = Reads Disabled
-		 *	   1 = Reads Enabled
-		 * [ 1: 1] Write Enable
-		 *	   0 = Writes Disabled
-		 *	   1 = Writes Enabled
-		 * [ 3: 2] Reserved
-		 * [ 4: 4] VGA Enable
-		 *	   0 = VGA matches Disabled
-		 *	   1 = matches all address < 64K and where A[9:0] is in the
-		 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
-		 * [ 5: 5] ISA Enable
-		 *	   0 = ISA matches Disabled
-		 *	   1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
-		 *	       from matching agains this base/limit pair
-		 * [11: 6] Reserved
-		 * [24:12] PCI I/O Base i
-		 *	   This field defines the start of PCI I/O region n
-		 * [31:25] Reserved
-		 */
-//		ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003,
-		ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
-		ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
-		ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
-
-		/* Config Base and Limit i Registers
-		 * F1:0xE0 i = 0
-		 * F1:0xE4 i = 1
-		 * F1:0xE8 i = 2
-		 * F1:0xEC i = 3
-		 * [ 0: 0] Read Enable
-		 *	   0 = Reads Disabled
-		 *	   1 = Reads Enabled
-		 * [ 1: 1] Write Enable
-		 *	   0 = Writes Disabled
-		 *	   1 = Writes Enabled
-		 * [ 2: 2] Device Number Compare Enable
-		 *	   0 = The ranges are based on bus number
-		 *	   1 = The ranges are ranges of devices on bus 0
-		 * [ 3: 3] Reserved
-		 * [ 6: 4] Destination Node
-		 *	   000 = Node 0
-		 *	   001 = Node 1
-		 *	   010 = Node 2
-		 *	   011 = Node 3
-		 *	   100 = Node 4
-		 *	   101 = Node 5
-		 *	   110 = Node 6
-		 *	   111 = Node 7
-		 * [ 7: 7] Reserved
-		 * [ 9: 8] Destination Link
-		 *	   00 = Link 0
-		 *	   01 = Link 1
-		 *	   10 = Link 2
-		 *	   11 - Reserved
-		 * [15:10] Reserved
-		 * [23:16] Bus Number Base i
-		 *	   This field defines the lowest bus number in configuration region i
-		 * [31:24] Bus Number Limit i
-		 *	   This field defines the highest bus number in configuration regin i
-		 */
-//		ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
-		ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
-		ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
-		ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
-	};
-
-	int max;
-	max = ARRAY_SIZE(register_values);
-	setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
deleted file mode 100644
index b7af9e2cf5..0000000000
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-//#define SYSTEM_TYPE 0	/* SERVER */
-#define SYSTEM_TYPE 1	/* DESKTOP */
-//#define SYSTEM_TYPE 2	/* MOBILE */
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <timestamp.h>
-#include <cpu/amd/model_10xxx_rev.h>
-#include <cpu/x86/bist.h>
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8712f/it8712f.h>
-#include <cpu/amd/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/amd/car.h>
-#include <southbridge/amd/common/reset.h>
-#include <southbridge/amd/sb700/sb700.h>
-#include <southbridge/amd/sb700/smbus.h>
-#include <northbridge/amd/amdfam10/raminit.h>
-#include <northbridge/amd/amdht/ht_wrapper.h>
-#include <cpu/amd/family_10h-family_15h/init_cpus.h>
-#include <arch/early_variables.h>
-#include <cbmem.h>
-#include <spd.h>
-#include <southbridge/amd/rs780/rs780.h>
-
-#include "cpu/amd/quadcore/quadcore.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
-#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
-
-int spd_read_byte(unsigned int device, unsigned int address);
-
-
-int spd_read_byte(u32 device, u32 address)
-{
-	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	struct sys_info *sysinfo = get_sysinfo();
-	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
-	u32 bsp_apicid = 0, val;
-	msr_t msr;
-
-	timestamp_init(timestamp_get());
-	timestamp_add_now(TS_START_ROMSTAGE);
-
-	if (!cpu_init_detectedx && boot_cpu()) {
-		/* Nothing special needs to be done to find bus 0 */
-		/* Allow the HT devices to be found */
-		/* mov bsp to bus 0xff when > 8 nodes */
-		set_bsp_node_CHtExtNodeCfgEn();
-		enumerate_ht_chain();
-		sb7xx_51xx_pci_port80();
-	}
-
-	post_code(0x30);
-
-	if (bist == 0) {
-		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
-		/* All cores run this but the BSP(node0,core0) is the only core that returns. */
-	}
-
-	post_code(0x32);
-
-	enable_rs780_dev8();
-	sb7xx_51xx_lpc_init();
-
-	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	ite_kill_watchdog(GPIO_DEV);
-
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	// Load MPB
-	val = cpuid_eax(1);
-	printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
-	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
-	printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
-	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
-	/* Setup sysinfo defaults */
-	set_sysinfo_in_ram(0);
-
-	update_microcode(val);
-
-	post_code(0x33);
-
-	cpuSetAMDMSR(0);
-	post_code(0x34);
-
-	amd_ht_init(sysinfo);
-	post_code(0x35);
-
-	/* Setup nodes PCI space and start core 0 AP init. */
-	finalize_node_setup(sysinfo);
-
-	/* Setup any mainboard PCI settings etc. */
-	setup_mb_resource_map();
-	post_code(0x36);
-
-	/* wait for all the APs core0 started by finalize_node_setup. */
-	/* FIXME: A bunch of cores are going to start output to serial at once.
-	   It would be nice to fixup prink spinlocks for ROM XIP mode.
-	   I think it could be done by putting the spinlock flag in the cache
-	   of the BSP located right after sysinfo.
-	 */
-	wait_all_core0_started();
-
- #if CONFIG(LOGICAL_CPUS)
-	/* Core0 on each node is configured. Now setup any additional cores. */
-	printk(BIOS_DEBUG, "start_other_cores()\n");
-	start_other_cores(bsp_apicid);
-	post_code(0x37);
-	wait_all_other_cores_started(bsp_apicid);
- #endif
-
-	post_code(0x38);
-
-	/* run _early_setup before soft-reset. */
-	rs780_early_setup();
-	sb7xx_51xx_early_setup();
-
- #if CONFIG(SET_FIDVID)
-	msr = rdmsr(MSR_COFVID_STS);
-	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
-
-	/* FIXME: The sb fid change may survive the warm reset and only
-	   need to be done once.*/
-	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
-	post_code(0x39);
-
-	if (!warm_reset_detect(0)) {			// BSP is node 0
-		init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
-	} else {
-		init_fidvid_stage2(bsp_apicid, 0);	// BSP is node 0
-	}
-
-	post_code(0x3A);
-
-	/* show final fid and vid */
-	msr = rdmsr(MSR_COFVID_STS);
-	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
- #endif
-
-	rs780_htinit();
-
-	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
-	if (!warm_reset_detect(0)) {
-		printk(BIOS_INFO, "...WARM RESET...\n\n\n");
-		soft_reset();
-		die("After soft_reset - shouldn't see this message!!!\n");
-	}
-
-	post_code(0x3B);
-
-	/* It's the time to set ctrl in sysinfo now; */
-	printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
-	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
-	post_code(0x40);
-
-	raminit_amdmct(sysinfo);
-
-	cbmem_initialize_empty();
-	post_code(0x41);
-
-	amdmct_cbmem_store_info(sysinfo);
-
-	sb7xx_51xx_before_pci_init();
-
-	post_code(0x42);
-}
-
-/**
- * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
- * Description:
- *	This routine is called every time a non-coherent chain is processed.
- *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
- *	swap list. The first part of the list controls the BUID assignment and the
- *	second part of the list provides the device to device linking.  Device orientation
- *	can be detected automatically, or explicitly.  See documentation for more details.
- *
- *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
- *	based on each device's unit count.
- *
- * Parameters:
- *	@param[in]  node   = The node on which this chain is located
- *	@param[in]  link   = The link on the host for this chain
- *	@param[out] List   = supply a pointer to a list
- */
-BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
-{
-#if !CONFIG(BOARD_ASUS_M4A785TM)
-	static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
-	/* If the BUID was adjusted in early_ht we need to do the manual override */
-	if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
-		printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
-		if ((node == 0) && (link == 0)) {	/* BSP SB link */
-			*List = swaplist;
-			return 1;
-		}
-	}
-#else
-	static const u8 swaplist[] = {0, 1, 0xFF, 0, 0xFF};
-	/* If the BUID was adjusted in early_ht we need to do the manual override */
-	if ((node == 0) && (link == 0)) {       /* BSP SB link */
-		*List = swaplist;
-		return 1;
-	}
-#endif
-
-	return 0;
-}
author	Arthur Heymans <arthur@aheymans.xyz>	2019-11-19 15:55:05 +0100
committer	Kyösti Mälkki <kyosti.malkki@gmail.com>	2019-11-20 18:58:43 +0000
commit	f2e42c4a8ec75c162251c72df8ac3da12e8a3eb9 (patch)
tree	fd5851ba2be3965df592355d02bce01f7dab0215 /src/mainboard/asus/m4a785-m
parent	ad983eeec76ecdb2aff4fb47baeee95ade012225 (diff)