Remove all AMD K8 boards

Platforms with LATE_CBMEM_INIT were agreed to be
removed with 4.7 release late 2017.

Change-Id: I0ecbb40f8c7ebdf68217f50af5624905d9005c64
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

11 files changed, 0 insertions, 1377 deletions

diff --git a/src/mainboard/asus/m2v/Kconfig b/src/mainboard/asus/m2v/Kconfig
deleted file mode 100644
index 26bfeef26f..0000000000
--- a/src/mainboard/asus/m2v/Kconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-if BOARD_ASUS_M2V
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_AMD_SOCKET_AM2
-	select DIMM_DDR2
-	select QRANK_DIMM_SUPPORT
-	select K8_HT_FREQ_1G_SUPPORT
-	select NORTHBRIDGE_AMD_AMDK8
-	select SOUTHBRIDGE_VIA_VT8237R
-	select SOUTHBRIDGE_VIA_K8T890
-	select SOUTHBRIDGE_VIA_SUBTYPE_K8T890
-	select SUPERIO_ITE_IT8712F
-	select HAVE_OPTION_TABLE
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_512
-	select HAVE_ACPI_RESUME
-	select HAVE_PIRQ_TABLE
-	select PIRQ_ROUTE
-	select HAVE_MP_TABLE
-	select SET_FIDVID
-
-config MAINBOARD_DIR
-	string
-	default asus/m2v
-
-config DCACHE_RAM_BASE
-	hex
-	default 0xcc000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x4000
-
-config APIC_ID_OFFSET
-	hex
-	default 0x10
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "M2V"
-
-config HW_MEM_HOLE_SIZEK
-	hex
-	default 0x0
-
-config MAX_CPUS
-	int
-	default 2
-
-config MAX_PHYSICAL_CPUS
-	int
-	default 1
-
-config HT_CHAIN_UNITID_BASE
-	hex
-	default 0x0
-
-config HT_CHAIN_END_UNITID_BASE
-	hex
-	default 0x20
-
-config IRQ_SLOT_COUNT
-	int
-	default 14
-
-endif # BOARD_ASUS_M2V
diff --git a/src/mainboard/asus/m2v/Kconfig.name b/src/mainboard/asus/m2v/Kconfig.name
deleted file mode 100644
index c0fc2f31a3..0000000000
--- a/src/mainboard/asus/m2v/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASUS_M2V
-	bool "M2V"
diff --git a/src/mainboard/asus/m2v/acpi_tables.c b/src/mainboard/asus/m2v/acpi_tables.c
deleted file mode 100644
index fce0fb6db2..0000000000
--- a/src/mainboard/asus/m2v/acpi_tables.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Written by Stefan Reinauer <stepan@openbios.org>.
- * ACPI FADT, FACS, and DSDT table support added by
- *
- * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
- * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
- * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8t890.h"
-#include "northbridge/amd/amdk8/acpi.h"
-#include <cpu/amd/powernow.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-void get_bus_conf(void)
-{
-	/* FIXME: implement this.  */
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	unsigned int gsi_base = 0x18;
-
-	/* Create all subtables for processors. */
-	current = acpi_create_madt_lapics(current);
-
-	/* Write SB IOAPIC. */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				VT8237R_APIC_ID, IO_APIC_ADDR, 0);
-
-	/* Write NB IOAPIC. */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);
-
-	/* IRQ9 ACPI active low. */
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
-
-	/* IRQ0 -> APIC IRQ2. */
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 0, 2, 0x0);
-
-	/* Create all subtables for processors. */
-	current = acpi_create_madt_lapic_nmis(current,
-			MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
-
-	return current;
-}
diff --git a/src/mainboard/asus/m2v/board_info.txt b/src/mainboard/asus/m2v/board_info.txt
deleted file mode 100644
index 1abcb5b361..0000000000
--- a/src/mainboard/asus/m2v/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Category: desktop
-Board URL: http://www.asus.com/Motherboards/AMD_AM2/M2V/
-ROM package: PLCC
-ROM protocol: LPC
-ROM socketed: y
-Flashrom support: y
-Release year: 2007
diff --git a/src/mainboard/asus/m2v/cmos.layout b/src/mainboard/asus/m2v/cmos.layout
deleted file mode 100644
index aae7ceb075..0000000000
--- a/src/mainboard/asus/m2v/cmos.layout
+++ /dev/null
@@ -1,52 +0,0 @@
-entries
-
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#392          3       r       0        unused
-395          1       e       1        hw_scrubber
-396          1       e       1        interleave_chip_selects
-397          2       e       8        max_mem_clock
-399         1       e       2        multi_core
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-440          4       e       9        slow_cpu
-444          1       e       1        nmi
-445          1       e       1        iommu
-456          1       e       1        ECC_memory
-728        256       h       0        user_data
-984         16       h       0        check_sum
-# Reserve the extended AMD configuration registers
-1000        24       r       0        amd_reserved
-
-
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     5     Notice
-6     6     Info
-6     7     Debug
-6     8     Spew
-8     0     DDR400
-8     1     DDR333
-8     2     DDR266
-8     3     DDR200
-9     0     off
-9     1     87.5%
-9     2     75.0%
-9     3     62.5%
-9     4     50.0%
-9     5     37.5%
-9     6     25.0%
-9     7     12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asus/m2v/devicetree.cb b/src/mainboard/asus/m2v/devicetree.cb
deleted file mode 100644
index 61d94bad3f..0000000000
--- a/src/mainboard/asus/m2v/devicetree.cb
+++ /dev/null
@@ -1,75 +0,0 @@
-chip northbridge/amd/amdk8/root_complex		# Root complex
-  device cpu_cluster 0 on			# APIC cluster
-    chip cpu/amd/socket_AM2			# CPU
-      device lapic 0 on end			# APIC
-    end
-  end
-  device domain 0 on			# PCI domain
-    subsystemid 0x1043 0 inherit
-    chip northbridge/amd/amdk8			# mc0
-      device pci 18.0 on			# Northbridge
-        # Devices on link 0, link 0 == LDT 0
-        chip southbridge/via/vt8237r		# Southbridge
-          register "ide0_enable" = "1"		# Enable IDE channel 0
-          register "ide1_enable" = "1"		# Enable IDE channel 1
-          register "ide0_80pin_cable" = "1"	# 80pin cable on IDE channel 0
-          register "ide1_80pin_cable" = "1"	# 80pin cable on IDE channel 1
-          register "fn_ctrl_lo" = "0xc0"	# Enable SB functions
-          register "fn_ctrl_hi" = "0x0d"	# Enable SB functions
-          device pci 0.0 on end			# HT
-          device pci f.1 on end			# IDE
-          device pci 11.0 on			# LPC
-            chip drivers/generic/generic	# DIMM 0-0-0
-              device i2c 50 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-0-1
-              device i2c 51 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-1-0
-              device i2c 52 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-1-1
-              device i2c 53 on end
-            end
-            chip superio/ite/it8712f		# Super I/O
-              device pnp 2e.0 on		# Floppy
-                io 0x60 = 0x3f0
-                irq 0x70 = 6
-                drq 0x74 = 2
-              end
-              device pnp 2e.1 on		# Com1
-                io 0x60 = 0x3f8
-                irq 0x70 = 4
-              end
-              device pnp 2e.2 off end		# Com2 (N/A on this board)
-              device pnp 2e.3 on		# Lpt1
-                io 0x60 = 0x378
-                irq 0x70 = 7
-                drq 0x74 = 3
-              end
-              device pnp 2e.4 on		# Environment controller
-                io 0x60 = 0xd00
-                io 0x62 = 0xc00
-                irq 0x70 = 0x00
-              end
-              device pnp 2e.5 off end		# PS/2 keyboard
-              device pnp 2e.6 off end		# PS/2 mouse
-              device pnp 2e.7 off end		# GPIO config
-              device pnp 2e.8 off end		# Midi port
-              device pnp 2e.9 off end		# Game port
-              device pnp 2e.a off end		# IR
-            end
-          end
-          device pci 12.0 off end		# VIA LAN (off, other chip used)
-          device pci 13.0 on end		# br
-          device pci 13.1 on end		# br2, need to have it here to discover it
-        end
-        chip southbridge/via/k8t890		# "Southbridge" K8T890
-        end
-      end
-      device pci 18.1 on end
-      device pci 18.2 on end
-      device pci 18.3 on end
-    end
-  end
-end
diff --git a/src/mainboard/asus/m2v/dsdt.asl b/src/mainboard/asus/m2v/dsdt.asl
deleted file mode 100644
index 760d5e214c..0000000000
--- a/src/mainboard/asus/m2v/dsdt.asl
+++ /dev/null
@@ -1,545 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- */
-
-#define LNKA INTA
-#define LNKB INTB
-#define LNKC INTC
-#define LNKD INTD
-
-/*
- * For simplicity map LNK[E-H] to LNK[A-D].
- * This also means we are 82C596 compatible.
- * Needs 0:11.0 0x46[4] set to 0.
- */
-#define LNKE INTA
-#define LNKF INTB
-#define LNKG INTC
-#define LNKH INTD
-
-DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE  ", "COREBOOT", 1)
-{
-	Name(APIC, 0)		// 0=>8259, 1=>IOAPIC
-
-	/* The _PIC method is called by the OS to choose between interrupt
-	 * routing via the i8259 interrupt controller or the APIC.
-	 *
-	 * _PIC is called with a parameter of 0 for i8259 configuration and
-	 * with a parameter of 1 for Local Apic/IOAPIC configuration.
-	 */
-
-	Method(_PIC, 1)
-	{
-		// Remember the OS' IRQ routing choice.
-		Store(Arg0, APIC)
-	}
-
-	/* _PR CPU0 is dynamically supplied by SSDT */
-
-	#include <southbridge/via/k8t890/acpi/sleepstates.asl>
-
-	/* Root of the bus hierarchy */
-	Scope (\_SB)
-	{
-		/* Top PCI device */
-		Device (PCI0)
-		{
-			Name (_HID, EisaId ("PNP0A03"))
-			Name (_ADR, 0x00180000)
-			Name (_BBN, 0x00)
-
-			Name (APRT, Package() {
-				/* AGP? */
-				Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 },
-				Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 },
-				Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x12 },
-				Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x13 },
-				/* PCIe graphics bridge */
-				Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B },
-				Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
-				Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
-				Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
-				/* PCIe bridge */
-				Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F },
-				Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 },
-				Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 },
-				Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B },
-				/* SATA */
-				Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x15 },
-				/* IDE */
-				Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x15 },
-				/* USB */
-				Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x14 },
-				Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x16 },
-				Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
-				Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x17 },
-				/* PCI bridge */
-				Package (0x04) { 0x0013FFFF, 0x00, 0x00, 0x14 },
-				Package (0x04) { 0x0013FFFF, 0x01, 0x00, 0x14 },
-				Package (0x04) { 0x0013FFFF, 0x02, 0x00, 0x14 },
-				Package (0x04) { 0x0013FFFF, 0x03, 0x00, 0x14 },
-			})
-			Name (PPRT, Package() {
-				/* ?? */
-				Package (0x04) { 0x0001FFFF, 0x00, LNKA, 0x00 },
-				Package (0x04) { 0x0001FFFF, 0x01, LNKB, 0x00 },
-				Package (0x04) { 0x0001FFFF, 0x02, LNKC, 0x00 },
-				Package (0x04) { 0x0001FFFF, 0x03, LNKD, 0x00 },
-				/* PCIe graphics bridge */
-				Package (0x04) { 0x0002FFFF, 0x00, LNKH, 0x00 },
-				Package (0x04) { 0x0002FFFF, 0x01, LNKH, 0x00 },
-				Package (0x04) { 0x0002FFFF, 0x02, LNKH, 0x00 },
-				Package (0x04) { 0x0002FFFF, 0x03, LNKH, 0x00 },
-				/* PCIe bridge */
-				Package (0x04) { 0x0003FFFF, 0x00, LNKH, 0x00 },
-				Package (0x04) { 0x0003FFFF, 0x01, LNKH, 0x00 },
-				Package (0x04) { 0x0003FFFF, 0x02, LNKH, 0x00 },
-				Package (0x04) { 0x0003FFFF, 0x03, LNKH, 0x00 },
-				/* SATA */
-				Package (0x04) { 0x000FFFFF, 0x01, LNKB, 0x00 },
-				/* USB */
-				Package (0x04) { 0x0010FFFF, 0x00, LNKA, 0x00 },
-				Package (0x04) { 0x0010FFFF, 0x01, LNKB, 0x00 },
-				Package (0x04) { 0x0010FFFF, 0x02, LNKC, 0x00 },
-				Package (0x04) { 0x0010FFFF, 0x03, LNKD, 0x00 },
-				/* PCI bridge */
-				Package (0x04) { 0x0013FFFF, 0x00, LNKD, 0x00 },
-				Package (0x04) { 0x0013FFFF, 0x01, LNKD, 0x00 },
-				Package (0x04) { 0x0013FFFF, 0x02, LNKD, 0x00 },
-				Package (0x04) { 0x0013FFFF, 0x03, LNKD, 0x00 },
-			})
-
-			/* PCI Routing Table */
-			Method (_PRT, 0, NotSerialized)
-			{
-				If (APIC)
-				{
-					Return (APRT)
-				}
-				Return (PPRT)
-			}
-
-			Device (PEGG)
-			{
-				Name (_ADR, 0x00020000)
-				Name (APRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
-				})
-				Name (PPRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
-					Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
-					Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
-					Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
-				})
-				Method (_PRT, 0, NotSerialized)
-				{
-					If (APIC)
-					{
-						Return (APRT)
-					}
-					Return (PPRT)
-				}
-			}
-
-			Device (PEX0)
-			{
-				Name (_ADR, 0x00030000)
-				Name (APRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
-				})
-				Name (PPRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
-					Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
-					Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
-					Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
-				})
-				Method (_PRT, 0, NotSerialized)
-				{
-					If (APIC)
-					{
-						Return (APRT)
-					}
-					Return (PPRT)
-				}
-			}
-
-			Device (PEX1)
-			{
-				Name (_ADR, 0x00030001)
-				Name (APRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },
-				})
-				Name (PPRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
-					Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
-					Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
-					Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
-				})
-				Method (_PRT, 0, NotSerialized)
-				{
-					If (APIC)
-					{
-						Return (APRT)
-					}
-					Return (PPRT)
-				}
-			}
-
-			Device (PEX2)
-			{
-				Name (_ADR, 0x00030002)
-				Name (APRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },
-				})
-				Name (PPRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
-					Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
-					Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
-					Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
-				})
-				Method (_PRT, 0, NotSerialized)
-				{
-					If (APIC)
-					{
-						Return (APRT)
-					}
-					Return (PPRT)
-				}
-			}
-
-			Device (PCI6)
-			{
-				Name (_ADR, 0x00130000)
-				Name (APRT, Package () {
-					Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x11 }, /* IRQ17 */
-				})
-				Name (PPRT, Package () {
-					Package (0x04) { 0x0001FFFF, 0x00, LNKB, 0x00 },
-				})
-				Method (_PRT, 0, NotSerialized)
-				{
-					If (APIC)
-					{
-						Return (APRT)
-					}
-					Return (PPRT)
-				}
-			}
-
-			Device (PCI7)
-			{
-				Name (_ADR, 0x00130001)
-				Name (APRT, Package () {
-					/* PCI slot 1 */
-					Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x10 },
-					Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x11 },
-					Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x12 },
-					Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x13 },
-
-					/* PCI slot 2 */
-					Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x11 },
-					Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x12 },
-					Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x13 },
-					Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x10 },
-
-					/* PCI slot 3 */
-					Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x12 },
-					Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x13 },
-					Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x10 },
-					Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x11 },
-
-					/* PCI slot 4 */
-					Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x13 },
-					Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x10 },
-					Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x11 },
-					Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x12 },
-				})
-				Name (PPRT, Package () {
-					/* PCI slot 1 */
-					Package (0x04) { 0x0006FFFF, 0x00, LNKA, 0x00 },
-					Package (0x04) { 0x0006FFFF, 0x01, LNKB, 0x00 },
-					Package (0x04) { 0x0006FFFF, 0x02, LNKC, 0x00 },
-					Package (0x04) { 0x0006FFFF, 0x03, LNKD, 0x00 },
-
-					/* PCI slot 2 */
-					Package (0x04) { 0x0007FFFF, 0x00, LNKB, 0x00 },
-					Package (0x04) { 0x0007FFFF, 0x01, LNKC, 0x00 },
-					Package (0x04) { 0x0007FFFF, 0x02, LNKD, 0x00 },
-					Package (0x04) { 0x0007FFFF, 0x03, LNKA, 0x00 },
-
-					/* PCI slot 3 */
-					Package (0x04) { 0x0008FFFF, 0x00, LNKC, 0x00 },
-					Package (0x04) { 0x0008FFFF, 0x01, LNKD, 0x00 },
-					Package (0x04) { 0x0008FFFF, 0x02, LNKA, 0x00 },
-					Package (0x04) { 0x0008FFFF, 0x03, LNKB, 0x00 },
-
-					/* PCI slot 4 */
-					Package (0x04) { 0x0009FFFF, 0x00, LNKD, 0x00 },
-					Package (0x04) { 0x0009FFFF, 0x01, LNKA, 0x00 },
-					Package (0x04) { 0x0009FFFF, 0x02, LNKB, 0x00 },
-					Package (0x04) { 0x0009FFFF, 0x03, LNKC, 0x00 },
-				})
-
-				Method (_PRT, 0, NotSerialized)
-				{
-					If (APIC)
-					{
-						Return (APRT)
-					}
-					Return (PPRT)
-				}
-			}
-
-			Device (SBRG) { /* southbridge */
-				Name (_ADR, 0x00110000)
-				OperationRegion (PCIC, PCI_Config, 0x0, 0x100)
-
-				/* PS/2 keyboard (seems to be important for WinXP install) */
-				Device (KBD)
-				{
-					Name (_HID, EisaId ("PNP0303"))
-					Method (_STA, 0, NotSerialized)
-					{
-						Return (0x0f)
-					}
-					Method (_CRS, 0, Serialized)
-					{
-						Name (TMP, ResourceTemplate () {
-							IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
-							IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
-							IRQNoFlags () {1}
-						})
-						Return (TMP)
-					}
-				}
-
-				/* PS/2 mouse */
-				Device (MOU)
-				{
-					Name (_HID, EisaId ("PNP0F13"))
-					Method (_STA, 0, NotSerialized)
-					{
-						Return (0x0f)
-					}
-					Method (_CRS, 0, Serialized)
-					{
-						Name (TMP, ResourceTemplate () {
-						     IRQNoFlags () {12}
-						})
-						Return (TMP)
-					}
-				}
-
-				/* Parallel port */
-				Device (LPT0)
-				{
-					Name (_HID, EisaId ("PNP0401"))
-					Method (_STA, 0, NotSerialized)
-					{
-						Return (0x0f)
-					}
-					Method (_CRS, 0, Serialized)
-					{
-						Name (TMP, ResourceTemplate () {
-							IO (Decode16, 0x0378, 0x0378, 0x01, 0x08)
-							IO (Decode16, 0x0778, 0x0778, 0x01, 0x08)
-							IRQNoFlags () {7}
-							DMA (Compatibility, NotBusMaster, Transfer8) {3}
-						})
-						Return (TMP)
-					}
-				}
-			}
-
-			Device(MBRS) {
-				Name (_HID, EisaId ("PNP0C02"))
-				Name (_UID, 0x01)
-
-				External(_CRS) /* Resource Template in SSDT */
-			}
-
-			External(TOM1) /* top of memory below 4GB */
-
-			Method(_CRS, 0, Serialized) {
-				Name(TMP, ResourceTemplate() {
-					WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
-						0x0000,             // Granularity
-						0x0000,             // Range Minimum
-						0x00FF,             // Range Maximum
-						0x0000,             // Translation Offset
-						0x0100,             // Length
-						,,
-					)
-					IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
-
-					WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-						0x0000,			/* address granularity */
-						0x0000,			/* range minimum */
-						0x0CF7,			/* range maximum */
-						0x0000,			/* translation */
-						0x0CF8			/* length */
-					)
-
-					WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-						0x0000,			/* address granularity */
-						0x0D00,			/* range minimum */
-						0xFFFF,			/* range maximum */
-						0x0000,			/* translation */
-						0xF300			/* length */
-					)
-
-					/* memory space for PCI BARs below 4GB */
-					Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
-				})
-				CreateDWordField(TMP, MMIO._BAS, MM1B)
-				CreateDWordField(TMP, MMIO._LEN, MM1L)
-				/*
-				 * Declare memory between TOM1 and 4GB as available
-				 * for PCI MMIO.
-				 *
-				 * Use ShiftLeft to avoid 64bit constant (for XP).
-				 * This will work even if the OS does 32bit arithmetic, as
-				 * 32bit (0x00000000 - TOM1) will wrap and give the same
-				 * result as 64bit (0x100000000 - TOM1).
-				 */
-				Store(TOM1, MM1B)
-				ShiftLeft(0x10000000, 4, Local0)
-				Subtract(Local0, TOM1, Local0)
-				Store(Local0, MM1L)
-
-				Return(TMP)
-			}
-		}
-
-		Field (PCI0.SBRG.PCIC, ByteAcc, NoLock, Preserve)
-		{
-			Offset (0x55),
-			/*
-			 * Offset 0x55:
-			 *    3-0: reserved
-			 *    7-4: PCI INTA# routing
-			 * Offset 0x56:
-			 *    3-0: PCI INTB# routing
-			 *    7-4: PCI INTC# routing
-			 * Offset 0x57:
-			 *    3-0: reserved
-			 *    7-4: PCI INTD# routing
-			 *
-			 * Valid values for routing link:
-			 * 0:                disabled
-			 * 2,8,13:           reserved
-			 * 1,3-7,9-12,14,15: corresponding irq
-			 */
-			    , 4,
-			PINA, 4,
-			PINB, 4,
-			PINC, 4,
-			    , 4,
-			PIND, 4,
-		}
-
-		Name(IRQB, ResourceTemplate(){
-			IRQ(Level,ActiveLow,Shared){15}
-		})
-
-		Name(IRQP, ResourceTemplate(){
-			IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 6, 7, 10, 11, 12}
-		})
-
-		/* adapted from ma78gm/dsdt.asl */
-#define PCI_INTX_DEV(intx, pinx, uid)					\
-		Device(intx) {						\
-			Name(_HID, EISAID("PNP0C0F"))			\
-			Name(_UID, uid)					\
-									\
-			Method(_STA, 0) {				\
-				if (pinx) {				\
-					Return(0x0B)			\
-				}					\
-				Return(0x09)				\
-			}						\
-									\
-			Method(_DIS ,0) {				\
-				Store(0, pinx)				\
-			}						\
-									\
-			Method(_PRS ,0) {				\
-				Return(IRQP)				\
-			}						\
-									\
-			Method(_CRS ,0) {				\
-				CreateWordField(IRQB, 1, IRQN)		\
-				ShiftLeft(1, pinx, IRQN)		\
-				Return(IRQB)				\
-			}						\
-									\
-			Method(_SRS, 1) {				\
-				CreateWordField(ARG0, 1, IRQM)		\
-									\
-				/* Use lowest available IRQ */		\
-				FindSetRightBit(IRQM, Local0)		\
-				if (Local0) {				\
-					Decrement(Local0)		\
-				}					\
-				Store(Local0, pinx)			\
-			}						\
-		}							\
-
-PCI_INTX_DEV(INTA, PINA, 1)
-PCI_INTX_DEV(INTB, PINB, 2)
-PCI_INTX_DEV(INTC, PINC, 3)
-PCI_INTX_DEV(INTD, PIND, 4)
-	}
-
-	Field (_SB.PCI0.SBRG.PCIC, ByteAcc, NoLock, Preserve)
-	{
-		Offset (0x94),
-		/* two LSB bits are blink rate */
-		LEDR,   2,
-	}
-
-	Method (_PTS, 1, NotSerialized)
-	{
-		/* blink power led while suspended */
-		Store (0x1, LEDR)
-	}
-
-	Method (_WAK, 1, NotSerialized)
-	{
-		/* stop power led blinking */
-		Store (0x0, LEDR)
-		/* wake OK */
-		Return(Package(0x02){0x00, 0x00})
-	}
-}
diff --git a/src/mainboard/asus/m2v/irq_tables.c b/src/mainboard/asus/m2v/irq_tables.c
deleted file mode 100644
index 18bebf545e..0000000000
--- a/src/mainboard/asus/m2v/irq_tables.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * IRQ Routing Table
- *
- * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
- */
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-#include <device/pci_ids.h>
-
-/* Free irqs are 3, 5, 10 and 11 */
-#define IRQBM ((1 << 3)|(1 << 5)|(1 << 10)|(1 << 11))
-
-#define LNKA 1
-#define LNKB 2
-#define LNKC 3
-#define LNKD 4
-
-/*
- * For simplicity map LNK[E-H] to LNK[A-D].
- * This also means we are 82C596 compatible.
- * Needs 0:11.0 0x46[4] set to 0.
- */
-#define LNKE 1
-#define LNKF 2
-#define LNKG 3
-#define LNKH 4
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE, /* u32 signature */
-	PIRQ_VERSION,   /* u16 version   */
-	32+16*CONFIG_IRQ_SLOT_COUNT,        /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
-	0,           /* Where the interrupt router lies (bus) */
-	(0x11 << 3)|0, /* Where the interrupt router lies (dev) */
-	0,           /* IRQs devoted exclusively to PCI usage */
-	PCI_VENDOR_ID_VIA,         /* Compatible Vendor (VIA) */
-	PCI_DEVICE_ID_VIA_82C596,  /* Compatible Device (82C596) */
-	0,           /* Miniport data */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x5f,        /*  u8 checksum, this has to be set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
-	{
-		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
-		/* peg bridge */
-		{0x00, (0x02 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x0, 0x0},
-		/* pcie bridge */
-		{0x00, (0x03 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x0, 0x0},
-		/* sata/ide */
-		{0x00, (0x0f << 3) | 0x0, {{0x00, 0x0000}, {LNKB, IRQBM}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-		/* usb */
-		{0x00, (0x10 << 3) | 0x0, {{LNKA, IRQBM}, {LNKB, IRQBM}, {LNKC, IRQBM}, {LNKD, IRQBM}}, 0x0, 0x0},
-		/* agp bus? */
-		{0x01, (0x00 << 3) | 0x0, {{LNKA, IRQBM}, {LNKB, IRQBM}, {LNKC, IRQBM}, {LNKD, IRQBM}}, 0x0, 0x0},
-		/* pcie graphics */
-		{0x02, (0x00 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x6, 0x0},
-		/* onboard pcie atl1 ethernet */
-		{0x03, (0x00 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x0, 0x0},
-		/* pcie slot */
-		{0x04, (0x00 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x5, 0x0},
-		/* onboard marvell mv6121 sata */
-		{0x05, (0x00 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x0, 0x0},
-		/* Azalia HDAC */
-		{0x06, (0x01 << 3) | 0x0, {{LNKB, IRQBM}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-		/* PCI slots */
-		{0x07, (0x06 << 3) | 0x0, {{LNKA, IRQBM}, {LNKB, IRQBM}, {LNKC, IRQBM}, {LNKD, IRQBM}}, 0x1, 0x0},
-		{0x07, (0x07 << 3) | 0x0, {{LNKB, IRQBM}, {LNKC, IRQBM}, {LNKD, IRQBM}, {LNKA, IRQBM}}, 0x2, 0x0},
-		{0x07, (0x08 << 3) | 0x0, {{LNKC, IRQBM}, {LNKD, IRQBM}, {LNKA, IRQBM}, {LNKB, IRQBM}}, 0x3, 0x0},
-		{0x07, (0x09 << 3) | 0x0, {{LNKD, IRQBM}, {LNKA, IRQBM}, {LNKB, IRQBM}, {LNKC, IRQBM}}, 0x4, 0x0},
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/asus/m2v/mainboard.c b/src/mainboard/asus/m2v/mainboard.c
deleted file mode 100644
index e16faebfae..0000000000
--- a/src/mainboard/asus/m2v/mainboard.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <console/console.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-
-u32 vt8237_ide_80pin_detect(struct device *dev)
-{
-	struct device *lpc_dev;
-	u16 acpi_io_base;
-	u32 gpio_in;
-	u32 res;
-
-	lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
-				PCI_DEVICE_ID_VIA_VT8237A_LPC, 0);
-	if (!lpc_dev)
-		return 0;
-
-	acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1;
-	if (!acpi_io_base)
-		return 0;
-
-	gpio_in = inl(acpi_io_base + 0x48);
-	/* bit 9 for primary port, clear if unconnected or 80-pin cable */
-	res  = gpio_in & (1 << 9) ? 0 : VT8237R_IDE0_80PIN_CABLE;
-	/* bit 4 for secondary port, clear if unconnected or 80-pin cable */
-	res |= gpio_in & (1 << 4) ? 0 : VT8237R_IDE1_80PIN_CABLE;
-
-	printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary",
-		res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40);
-	printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary",
-		res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40);
-
-	return res;
-}
diff --git a/src/mainboard/asus/m2v/mptable.c b/src/mainboard/asus/m2v/mptable.c
deleted file mode 100644
index 8de77ccdb5..0000000000
--- a/src/mainboard/asus/m2v/mptable.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <stdint.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8t890.h"
-
-static void smp_write_intsrc_pci(struct mp_config_table *mc,
-	unsigned char srcbus, unsigned char srcbusirq,
-	unsigned char dstapic, unsigned char dstirq)
-{
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
-			srcbus, srcbusirq, dstapic, dstirq);
-}
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	int bus_isa;
-
-	mc = (void*)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-	smp_write_processors(mc);
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-	/* I/O APICs:	APIC ID	Version	State		Address */
-	smp_write_ioapic(mc, VT8237R_APIC_ID, 0x3, VIO_APIC_VADDR);
-	smp_write_ioapic(mc, K8T890_APIC_ID, 0x3, (void*)K8T890_APIC_BASE);
-
-	mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
-
-	/* agp? bridge */
-	smp_write_intsrc_pci(mc, 0,  (0x1 << 2) | 0, VT8237R_APIC_ID, 0x10);
-	smp_write_intsrc_pci(mc, 0,  (0x1 << 2) | 1, VT8237R_APIC_ID, 0x11);
-	smp_write_intsrc_pci(mc, 0,  (0x1 << 2) | 2, VT8237R_APIC_ID, 0x12);
-	smp_write_intsrc_pci(mc, 0,  (0x1 << 2) | 3, VT8237R_APIC_ID, 0x13);
-
-	/* peg bridge */
-	smp_write_intsrc_pci(mc, 0,  (0x2 << 2) | 0, K8T890_APIC_ID, 0x3);
-	smp_write_intsrc_pci(mc, 0,  (0x2 << 2) | 1, K8T890_APIC_ID, 0x3);
-	smp_write_intsrc_pci(mc, 0,  (0x2 << 2) | 2, K8T890_APIC_ID, 0x3);
-	smp_write_intsrc_pci(mc, 0,  (0x2 << 2) | 3, K8T890_APIC_ID, 0x3);
-
-	/* pex bridge */
-	smp_write_intsrc_pci(mc, 0,  (0x3 << 2) | 0, K8T890_APIC_ID, 0x7);
-	smp_write_intsrc_pci(mc, 0,  (0x3 << 2) | 1, K8T890_APIC_ID, 0xb);
-	smp_write_intsrc_pci(mc, 0,  (0x3 << 2) | 2, K8T890_APIC_ID, 0xf);
-	smp_write_intsrc_pci(mc, 0,  (0x3 << 2) | 3, K8T890_APIC_ID, 0x13);
-
-	/* SATA / IDE */
-	smp_write_intsrc_pci(mc, 0,  (0xf << 2) | 0, VT8237R_APIC_ID, 0x15);
-
-	/* USB */
-	smp_write_intsrc_pci(mc, 0,  (0x10 << 2) | 0, VT8237R_APIC_ID, 0x14);
-	smp_write_intsrc_pci(mc, 0,  (0x10 << 2) | 1, VT8237R_APIC_ID, 0x16);
-	smp_write_intsrc_pci(mc, 0,  (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15);
-	smp_write_intsrc_pci(mc, 0,  (0x10 << 2) | 3, VT8237R_APIC_ID, 0x17);
-
-	/* PCIE graphics */
-	smp_write_intsrc_pci(mc, 2,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x0);
-	smp_write_intsrc_pci(mc, 2,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x1);
-	smp_write_intsrc_pci(mc, 2,  (0x00 << 2) | 2, K8T890_APIC_ID, 0x2);
-	smp_write_intsrc_pci(mc, 2,  (0x00 << 2) | 3, K8T890_APIC_ID, 0x3);
-
-	/* onboard PCIE atl1 ethernet */
-	smp_write_intsrc_pci(mc, 3,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x4);
-	smp_write_intsrc_pci(mc, 3,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x5);
-	smp_write_intsrc_pci(mc, 3,  (0x00 << 2) | 2, K8T890_APIC_ID, 0x6);
-	smp_write_intsrc_pci(mc, 3,  (0x00 << 2) | 3, K8T890_APIC_ID, 0x7);
-
-	/* PCIE slot */
-	smp_write_intsrc_pci(mc, 4,  (0x00 << 2) | 0, K8T890_APIC_ID, 0x8);
-	smp_write_intsrc_pci(mc, 4,  (0x00 << 2) | 1, K8T890_APIC_ID, 0x9);
-	smp_write_intsrc_pci(mc, 4,  (0x00 << 2) | 2, K8T890_APIC_ID, 0xa);
-	smp_write_intsrc_pci(mc, 4,  (0x00 << 2) | 3, K8T890_APIC_ID, 0xb);
-
-	/* onboard marvell mv6121 sata */
-	smp_write_intsrc_pci(mc, 5,  (0x00 << 2) | 0, K8T890_APIC_ID, 0xc);
-	smp_write_intsrc_pci(mc, 5,  (0x00 << 2) | 1, K8T890_APIC_ID, 0xd);
-	smp_write_intsrc_pci(mc, 5,  (0x00 << 2) | 2, K8T890_APIC_ID, 0xe);
-	smp_write_intsrc_pci(mc, 5,  (0x00 << 2) | 3, K8T890_APIC_ID, 0xf);
-
-	/* azalia HDCA */
-	smp_write_intsrc_pci(mc, 6,  (0x01 << 2) | 0, VT8237R_APIC_ID, 0x11);
-
-	/* pci slot 1 */
-	smp_write_intsrc_pci(mc, 7, (6 << 2) | 0, VT8237R_APIC_ID, 0x10);
-	smp_write_intsrc_pci(mc, 7, (6 << 2) | 1, VT8237R_APIC_ID, 0x11);
-	smp_write_intsrc_pci(mc, 7, (6 << 2) | 2, VT8237R_APIC_ID, 0x12);
-	smp_write_intsrc_pci(mc, 7, (6 << 2) | 3, VT8237R_APIC_ID, 0x13);
-
-	/* pci slot 2 */
-	smp_write_intsrc_pci(mc, 7, (7 << 2) | 0, VT8237R_APIC_ID, 0x11);
-	smp_write_intsrc_pci(mc, 7, (7 << 2) | 1, VT8237R_APIC_ID, 0x12);
-	smp_write_intsrc_pci(mc, 7, (7 << 2) | 2, VT8237R_APIC_ID, 0x13);
-	smp_write_intsrc_pci(mc, 7, (7 << 2) | 3, VT8237R_APIC_ID, 0x10);
-
-	/* pci slot 3 */
-	smp_write_intsrc_pci(mc, 7, (8 << 2) | 0, VT8237R_APIC_ID, 0x12);
-	smp_write_intsrc_pci(mc, 7, (8 << 2) | 1, VT8237R_APIC_ID, 0x13);
-	smp_write_intsrc_pci(mc, 7, (8 << 2) | 2, VT8237R_APIC_ID, 0x10);
-	smp_write_intsrc_pci(mc, 7, (8 << 2) | 3, VT8237R_APIC_ID, 0x11);
-
-	/* pci slot 4 */
-	smp_write_intsrc_pci(mc, 7, (9 << 2) | 0, VT8237R_APIC_ID, 0x13);
-	smp_write_intsrc_pci(mc, 7, (9 << 2) | 1, VT8237R_APIC_ID, 0x10);
-	smp_write_intsrc_pci(mc, 7, (9 << 2) | 2, VT8237R_APIC_ID, 0x11);
-	smp_write_intsrc_pci(mc, 7, (9 << 2) | 3, VT8237R_APIC_ID, 0x12);
-
-	/* Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
-	mptable_lintsrc(mc, 0);
-	/* There is no extension information... */
-
-	/* Compute the checksums. */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);
-	return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
deleted file mode 100644
index d49f231f75..0000000000
--- a/src/mainboard/asus/m2v/romstage.c
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2006 MSI
- * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
- * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-unsigned int get_sbdn(unsigned bus);
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <halt.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8712f/it8712f.h>
-#include <southbridge/via/vt8237r/vt8237r.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include <spd.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
-#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
-#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO)
-
-#define IT8712F_GPIO_BASE		0x0a20
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "southbridge/via/k8t890/early_car.c"
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-
-void do_soft_reset(void)
-{
-	uint8_t tmp;
-
-	set_bios_reset();
-	printk(BIOS_DEBUG, "soft reset\n");
-
-	/* PCI reset */
-	tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
-	tmp |= 0x01;
-	/* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
-	pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
-
-	halt();
-}
-
-unsigned int get_sbdn(unsigned bus)
-{
-	pci_devfn_t dev;
-
-	dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
-					PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
-	return (dev >> 15) & 0x1f;
-}
-
-struct gpio_init_val {
-	u8 addr;
-	u8 val;
-};
-
-static const struct gpio_init_val gpio_init_data[] = {
-	/* multi-function pin selection */
-	{ 0x25, 0x00 },
-	{ 0x28, 0x00 }, /* gp46 is infrared receive input */
-	{ 0x29, 0x40 }, /* reserved value?!? */
-	{ 0x2a, 0x00 },
-	{ 0x2c, 0x1d }, /* pin91 is VIN7 instead of PCIRSTIN# */
-	/* gpio i/o port base */
-	{ 0x62, IT8712F_GPIO_BASE >> 8 },
-	{ 0x63, IT8712F_GPIO_BASE & 0xff },
-	/* 0xb8 - 0xbc: gpio pull-up enable */
-	{ 0xb8, 0x00 },
-	/* 0xc0 - 0xc4: gpio alternate function select */
-	{ 0xc0, 0x00 },
-	{ 0xc3, 0x00 },
-	{ 0xc4, 0xc0 },
-	/* 0xc8 - 0xcc: gpio output enable */
-	{ 0xc8, 0x00 },
-	{ 0xcb, 0x00 },
-	{ 0xcc, 0xc0 },
-	/* end of list */
-	{ 0, 0 },
-};
-
-static void m2v_it8712f_gpio_init(void)
-{
-	const struct gpio_init_val *giv;
-
-	printk(BIOS_SPEW, "it8712f gpio init...\n");
-
-	/*
-	 * it8712f gpio config
-	 *
-	 * Most importantly this switches pin 91 from
-	 * PCIRSTIN# to VIN7.
-	 * Note that only PCIRST3# and PCIRST5# are affected
-	 * by PCIRSTIN#, the PCIRST1#, PCIRST2#, PCIRST4# are always
-	 * direct buffers of #LRESET (low pin count bus reset).
-	 * If this is not done All PCIRST are in reset state and the
-	 * pcie slots don't initialize.
-	 *
-	 * pci reset handling:
-	 * pin 91: VIN7 (alternate PCIRSTIN#)
-	 * pin 48: PCIRST5# / gpio port 5 bit 0
-	 * pin 84: PCIRST4# / gpio port 1 bit 0
-	 * pin 31: PCIRST1# / gpio port 1 bit 4
-	 * pin 33: PCIRST2# / gpio port 1 bit 2
-	 * pin 34: PCIRST3# / gpio port 1 bit 1
-	 *
-	 * PCIRST[0-5]# are connected as follows:
-	 * pcirst1# -> pci bus
-	 * pcirst2# -> ide bus
-	 * pcirst3# -> pcie devices
-	 * pcirst4# -> pcie graphics
-	 * pcirst5# -> maybe n/c (untested)
-	 *
-	 * For software control of PCIRST[1-5]#:
-	 * 0x2a = 0x17 (deselect pcirst# hardwiring, enable 0x25 control)
-	 * 0x25 = 0x17 (select gpio function)
-	 * 0xc0 = 0x17, 0xc8 = 0x17 gpio port 1 select & output enable
-	 * 0xc4 = 0xc1, 0xcc = 0xc1 gpio port 5 select & output enable
-	 */
-	giv = gpio_init_data;
-	while (giv->addr) {
-		printk(BIOS_SPEW, "it8712f gpio: %02x=%02x\n",
-				giv->addr, giv->val);
-		ite_reg_write(IT8712F_GPIO, giv->addr, giv->val);
-		giv++;
-	}
-
-	printk(BIOS_INFO, "it8712f gpio: Setting DDR2 voltage to 1.80V\n");
-	/*
-	 * upper two bits of gpio_base+4 control ddr2 voltage:
-	 * 11: 1.80V
-	 * 01: 1.85V
-	 * 10: 1.90V
-	 * 00: 1.95V
-	 *
-	 * The lower six bits are inputs and normally read back as 1
-	 * (except bit 2, which seems rather random).
-	 */
-	outb(0xff, IT8712F_GPIO_BASE+4);
-}
-
-static void m2v_bus_init(void)
-{
-	pci_devfn_t dev;
-
-	printk(BIOS_SPEW, "m2v_bus_init\n");
-
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-				PCI_DEVICE_ID_VIA_K8T890CF_0), 0);
-	pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01);
-
-	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
-				PCI_DEVICE_ID_VIA_K8T890CF_5), 0);
-	/*
-	 * bit | meaning
-	 * 6   | 0: hide scratch register function 0:0.6 (we don't use it)
-	 * 5   | 1: enable pcie bridge 0:2.0
-	 * 4   | 0: hide   pcie bridge 0:3.3 (not connected)
-	 * 3   | 1: enable pcie bridge 0:3.2
-	 * 2   | 1: enable pcie bridge 0:3.1
-	 * 1   | 1: enable pcie bridge 0:3.0
-	 */
-	pci_write_config8(dev, 0xf0, 0x2e);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	static const uint16_t spd_addr[] = {
-		// Node 0
-		DIMM0, DIMM2, 0, 0,
-		DIMM1, DIMM3, 0, 0,
-		// Node 1
-		DIMM4, DIMM6, 0, 0,
-		DIMM5, DIMM7, 0, 0,
-	};
-	unsigned bsp_apicid = 0;
-	int needs_reset = 0;
-	struct sys_info *sysinfo = &sysinfo_car;
-
-	ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
-	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	ite_kill_watchdog(GPIO_DEV);
-	console_init();
-	enable_rom_decode();
-	m2v_bus_init();
-	m2v_it8712f_gpio_init();
-	ite_enable_3vsbsw(GPIO_DEV);
-
-	printk(BIOS_INFO, "now booting...\n");
-
-	if (bist == 0)
-		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
-	/* Halt if there was a built in self test failure. */
-	report_bist_failure(bist);
-	setup_default_resource_map();
-	setup_coherent_ht_domain();
-	wait_all_core0_started();
-
-	printk(BIOS_INFO, "now booting... All core 0 started\n");
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
-	/* It is said that we should start core1 after all core0 launched. */
-	start_other_cores();
-	wait_all_other_cores_started(bsp_apicid);
-#endif
-	init_timer();
-	ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
-
-	needs_reset = optimize_link_coherent_ht();
-	printk(BIOS_DEBUG, "%02x", needs_reset);
-	needs_reset |= optimize_link_incoherent_ht(sysinfo);
-	printk(BIOS_DEBUG, "%02x", needs_reset);
-	needs_reset |= k8t890_early_setup_ht();
-	printk(BIOS_DEBUG, "%02x", needs_reset);
-
-	if (needs_reset) {
-		printk(BIOS_DEBUG, "ht reset -\n");
-		soft_reset();
-		printk(BIOS_DEBUG, "FAILED!\n");
-	}
-
-	/* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
-	/* allow LDT STOP asserts */
-	vt8237_sb_enable_fid_vid();
-
-	enable_fid_change();
-	printk(BIOS_DEBUG, "after enable_fid_change\n");
-
-	init_fidvid_bsp(bsp_apicid);
-
-	/* Stop the APs so we can start them later in init. */
-	allow_all_aps_stop(bsp_apicid);
-
-	/* It's the time to set ctrl now. */
-	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-	enable_smbus();
-	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-}