diff options
| author | Tobias Diedrich <ranma+coreboot@tdiedrich.de> | 2010-11-24 20:03:09 +0000 |
|---|---|---|
| committer | Tobias Diedrich <ranma@tdiedrich.de> | 2010-11-24 20:03:09 +0000 |
| commit | 48ae6086da64eb260c6eed676c593cdcd0957fbf (patch) | |
| tree | f70d55ae2a05576cd988c9ee07c770b49dae1617 /src/mainboard/asus/m2v/dsdt.asl | |
| parent | ba9f0b30fb3d2081e30c8957194f3a0a202bc2ef (diff) | |
S3 support for ASUS M2V
This adds the board-specific parts for S3 support on the M2V board.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6122 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/asus/m2v/dsdt.asl')
| -rw-r--r-- | src/mainboard/asus/m2v/dsdt.asl | 31 |
1 files changed, 27 insertions, 4 deletions
diff --git a/src/mainboard/asus/m2v/dsdt.asl b/src/mainboard/asus/m2v/dsdt.asl index 959e5a7990..40bde8f38e 100644 --- a/src/mainboard/asus/m2v/dsdt.asl +++ b/src/mainboard/asus/m2v/dsdt.asl @@ -59,10 +59,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) /* _PR CPU0 is dynamically supplied by SSDT */ - /* For now only define 2 power states: + /* We define 3 power states: * - S0 which is fully on + * - S3 which is suspend to ram * - S5 which is soft off - * Any others would involve declaring the wake up methods. * * Package contents: * ofs len desc @@ -73,6 +73,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) * 2 2 Reserved */ Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S3, Package () { 0x01, 0x01, 0x00, 0x00 }) Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) /* Root of the bus hierarchy */ @@ -341,6 +342,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) Device (SBRG) { /* southbridge */ Name (_ADR, 0x00110000) + OperationRegion (PCIC, PCI_Config, 0x0, 0x100) /* PS/2 keyboard (seems to be important for WinXP install) */ Device (KBD) @@ -459,9 +461,9 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) } } - OperationRegion (PCI0.SBRG.SBR1, PCI_Config, 0x55, 0x03) - Field (PCI0.SBRG.SBR1, ByteAcc, NoLock, Preserve) + Field (PCI0.SBRG.PCIC, ByteAcc, NoLock, Preserve) { + Offset (0x55), /* * Offset 0x55: * 3-0: reserved @@ -538,4 +540,25 @@ PCI_INTX_DEV(INTB, PINB, 2) PCI_INTX_DEV(INTC, PINC, 3) PCI_INTX_DEV(INTD, PIND, 4) } + + Field (_SB.PCI0.SBRG.PCIC, ByteAcc, NoLock, Preserve) + { + Offset (0x94), + /* two LSB bits are blink rate */ + LEDR, 2, + } + + Method (_PTS, 1, NotSerialized) + { + /* blink power led while suspended */ + Store (0x1, LEDR) + } + + Method (_WAK, 1, NotSerialized) + { + /* stop power led blinking */ + Store (0x0, LEDR) + /* wake OK */ + Return(Package(0x02){0x00, 0x00}) + } } |