diff options
author | Rudolf Marek <r.marek@assembler.cz> | 2008-12-23 17:34:15 +0000 |
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committer | Rudolf Marek <r.marek@assembler.cz> | 2008-12-23 17:34:15 +0000 |
commit | 79e532560c63d5ea095aaeb218443964bbceccae (patch) | |
tree | ed92a7ff038852caac5552f034e9f3211fe3407f /src/mainboard/asus/m2v-mx_se/dsdt.asl | |
parent | 33f9633184ddc84151ab3685725d13448cdec232 (diff) |
The attached patch adds missing bits to ACPI to make Windows XP and Windows Vista happy.
The FADT bootarch flags
Blacklists MSI for this chipset (maybe not needed)
Adds modified amdk8_util.asl
Adds the SSDT table to chain of tables
Aligns the FACS correctly (this should be done for other boards)
Adds the _CRS method to Asus M2V-MX SE acpi DSDT.
Fixes the FACS table length.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/asus/m2v-mx_se/dsdt.asl')
-rw-r--r-- | src/mainboard/asus/m2v-mx_se/dsdt.asl | 41 |
1 files changed, 40 insertions, 1 deletions
diff --git a/src/mainboard/asus/m2v-mx_se/dsdt.asl b/src/mainboard/asus/m2v-mx_se/dsdt.asl index ac32980531..61d34f2714 100644 --- a/src/mainboard/asus/m2v-mx_se/dsdt.asl +++ b/src/mainboard/asus/m2v-mx_se/dsdt.asl @@ -22,6 +22,9 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) { + Include ("amdk8_util.asl") + + /* Define the main processor.*/ Scope (\_PR) { @@ -47,9 +50,45 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1) Name (_ADR, 0x00) Name (_UID, 0x00) Name (_BBN, 0x00) + + External (BUSN) + External (MMIO) + External (PCIO) + External (SBLK) + External (TOM1) + External (HCLK) + External (SBDN) + External (HCDN) + + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, + 0x0CF8, // Address Range Minimum + 0x0CF8, // Address Range Maximum + 0x01, // Address Alignment + 0x08, // Address Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Address Space Granularity + 0x0000, // Address Range Minimum + 0x0CF7, // Address Range Maximum + 0x0000, // Address Translation Offset + 0x0CF8, // Address Length + ,, , TypeStatic) + }) + /* Methods bellow use SSDT to get actual MMIO regs + The IO ports are from 0xd00, optionally an VGA, + otherwise the info from MMIO is used. + */ + Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1) + Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2) + Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3) + Return (Local3) + } /* PCI Routing Table */ - /* aaa */ Name (_PRT, Package () { Package (0x04) { 0x000F0000, 0x01, 0x00, 0x15 }, /* 0xf SATA IRQ 21 */ Package (0x04) { 0x000F0001, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */ |