mainboard/asus/kgpe-d16: Add initial support for the KGPE-D16

As of this commit S3 suspend does not work on any K10 boards,
including this board.

Change-Id: Idd3971422fb2473bff7c60fe8d8161d6e20808ed
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11946
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 81 insertions, 0 deletions

diff --git a/src/mainboard/asus/kgpe-d16/mainboard.c b/src/mainboard/asus/kgpe-d16/mainboard.c
new file mode 100644
index 0000000000..47ede34098
--- /dev/null
+++ b/src/mainboard/asus/kgpe-d16/mainboard.c
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include <southbridge/amd/sb700/sb700.h>
+#include <southbridge/amd/sr5650/cmn.h>
+
+
+void set_pcie_reset(void);
+void set_pcie_dereset(void);
+
+void set_pcie_reset(void)
+{
+	device_t pcie_core_dev;
+
+	pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828);
+	set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x00000028);
+}
+
+void set_pcie_dereset(void)
+{
+	device_t pcie_core_dev;
+
+	pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F);
+	set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x000000FF, 0x0000006F);
+}
+
+/*************************************************
+* enable the dedicated function in kgpe-d16 board.
+* This function is called earlier than sr5650_enable.
+*************************************************/
+static void mainboard_enable(device_t dev)
+{
+	printk(BIOS_INFO, "Mainboard KGPE-D16 Enable. dev=0x%p\n", dev);
+
+	msr_t msr, msr2;
+
+	/* TOP_MEM: the top of DRAM below 4G */
+	msr = rdmsr(TOP_MEM);
+	printk
+	    (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+	     __func__, msr.lo, msr.hi);
+
+	/* TOP_MEM2: the top of DRAM above 4G */
+	msr2 = rdmsr(TOP_MEM2);
+	printk
+	    (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+	     __func__, msr2.lo, msr2.hi);
+
+	set_pcie_dereset();
+	/* get_ide_dma66(); */
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};