mainboards: Add support for the Asus KFSN4-DRE series of motherboards

Status:
Tested with KFSN4-DRE PCB v1.04G
Booted Ubuntu Linux 14.04 and all onboard peripherals appear to work.
Dual Opteron 8347 CPUs tested with 8GB RAM (4GB per bank).
Dual Opteron 8356 CPUs tested with 1GB RAM in slot A1.
AMD PowerNow! functions correctly via ACPI.
Video, network, USB, SATA, and serial have received thorough testing.
Tested with KFSN4-DRE PCB v1.05G
Single Opteron 2419 CPU tested with 1GB RAM in slot A1.
Booted to PXE configuration menu; not tested further.

Known issues:
RAM initialization is a bit flaky with multiple high-density modules;
this could be a generic MCT training issue but is probably bad hardware.
The XGI Volari option ROM crashes SeaBIOS v1.7.5, but the video device
works after Linux boots and initializes the device.
Suspend/resume functions at the S1 level but sometimes hangs on resume.
Wake on LAN can be flaky; the strap(s) needed to have WoL work on power
application were not physically installed by ASUS so the board needs to
boot at least once after power application before it will work.

Change-Id: I0709f822eea8ed877f55db9443143028a5400472
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8270
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)

1 files changed, 50 insertions, 0 deletions

diff --git a/src/mainboard/asus/kfsn4-dre/spd_notes.txt b/src/mainboard/asus/kfsn4-dre/spd_notes.txt
new file mode 100644
index 0000000000..ff49c18518
--- /dev/null
+++ b/src/mainboard/asus/kfsn4-dre/spd_notes.txt
@@ -0,0 +1,50 @@
+====================================================================================================
+SPD mux
+====================================================================================================
+
+DIMM_A1 SDA signal traced to U6 pin 1
+Destructive testing of failed board (removal of U7 northbridge!) yielded the following information:
+U6 S0 <--> U7 W2
+U6 S1 <--> U7 W3
+
+Proprietary BIOS enables the SPD during POST with:
+S0: LOW
+S1: LOW
+
+then temporarily switches to:
+S0: LOW
+S1: HIGH
+
+then switches to runtime mode with:
+S0: HIGH
+S1: LOW
+
+After probing with a custom GPIO-flipping tool under Linux the following GPIO mappings were found:
+CK804 pin W2 <--> GPIO43
+CK804 pin W3 <--> GPIO44
+
+====================================================================================================
+Other hardware
+====================================================================================================
+
+Power LED (-) is connected to U15 (SuperIO) pin 64 via U4 pins 5,6 and a small MOSFET
+ID LED (-) is connected to a ??? via U4 pins 1,2,3,4 and U77 pins 5,6
+It appears that setting U15 (SuperIO) pin 88 LOW will override the ID LED and force it ON
+
+PCIe slot WAKE# connects to U7 pin E23 (PCIE_WAKE#)
+
+CPU_WARN1 is driven by (???) via a simple buffer (U13 pin 10)
+MEM_WARN1 is driven by U7 pin AD3 (CPUVDD_EN) via a simple buffer (U101 pin 3)
+
+U7 pin AK3 is disconnected (routed to unpopulated capacitor/resistor)
+PU1 pin 37 (VDDPWRGD) drives U7 pin AJ4 (CPU_VLD)
+A small MOSFET directly above another small MOSFET directly above the right-hand edge of the PCIe slot drives U7 pin AK5 (HT_VLD)
+
+When > Barcelona CPU installed on PCB rev 1.04G:
+U7 pin AK4 (MEM_VLD): HIGH
+PU1 pin 37:           LOW
+U7 pin AK5:           LOW
+
+HyperTransport 1.2V supply appears to be generated by a linear regulator containing Q191 and downconverting the CK804 1.5V supply
+The enable pin appears to be tied to AUX_PANEL pin 1 (+5VSB) via a resistor
+Through two MOSFETs the HT supply enable pin is tied to U7 pin AE3 (HTVDD_EN)