diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-05-17 16:24:31 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-20 17:48:43 +0000 |
| commit | ee5b24d232fea4bf6f097463b38f43f3e6bc9e29 (patch) | |
| tree | ef2ed10cea00b223c302aa82257e4a3c9933a70f /src/mainboard/asus/h61-series/variants | |
| parent | 741856f7c8d1364444c98954a7efd67aa8fc5098 (diff) | |
mb/asus/p8h61-m_lx: Switch to overridetree setup
Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M LX
remains identical when not adding the .config file in it.
Change-Id: I3142773e8c8f11f27f7926933097ffde8ba241e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54390
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asus/h61-series/variants')
| -rw-r--r-- | src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb (renamed from src/mainboard/asus/h61-series/variants/p8h61-m_lx/devicetree.cb) | 32 |
1 files changed, 1 insertions, 31 deletions
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/devicetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb index 05b8e38f82..aa9f8c81b9 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/devicetree.cb +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/overridetree.cb @@ -1,36 +1,11 @@ ## SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/sandybridge - device cpu_cluster 0 on - chip cpu/intel/model_206ax - register "acpi_c1" = "1" - register "acpi_c2" = "3" - register "acpi_c3" = "5" - device lapic 0 on end - device lapic 0xacac off end - end - end - device domain 0 on subsystemid 0x1043 0x844d inherit - - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe bridge for discrete graphics - device pci 02.0 on end # VGA controller - chip southbridge/intel/bd82x6x - register "c2_latency" = "0x0065" register "gen1_dec" = "0x00000295" # Super I/O HWM - register "sata_port_map" = "0x33" - register "spi_lvscc" = "0x2005" - register "spi_uvscc" = "0x2005" - device pci 16.0 on end # Management Engine interface 1 - device pci 16.1 off end # Management Engine interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 device pci 1b.0 on # HD audio controller subsystemid 0x1043 0x8445 end @@ -48,8 +23,7 @@ chip northbridge/intel/sandybridge device pci 1c.5 off end # Unused PCIe port device pci 1c.6 off end # Unused PCIe port device pci 1c.7 off end # Unused PCIe port - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy @@ -106,10 +80,6 @@ chip northbridge/intel/sandybridge device pnp 2e.17 off end # GPIOA end end - device pci 1f.2 on end # SATA controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA controller 2 - device pci 1f.6 off end # Thermal end end end |