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authorMartin Roth <martinroth@google.com>2017-06-24 21:45:13 -0600
committerMartin Roth <martinroth@google.com>2017-07-06 00:19:48 +0000
commitf95911ad3765c0f94db241b0c95a6c0a8c608077 (patch)
tree9ba34618cff9bbc021348458468d1de0feeaa4b2 /src/mainboard/asus/f2a85-m
parent1bf55b4070bef2be8259f3153cade27121127b4a (diff)
mainboard/[a-e]: add IS_ENABLED() around Kconfig symbol references
Change-Id: Icca8bac5e67f83dfc5a8f5ef1cb87c6432e0a236 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/asus/f2a85-m')
-rw-r--r--src/mainboard/asus/f2a85-m/acpi/routing.asl2
-rw-r--r--src/mainboard/asus/f2a85-m/buildOpts.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl
index cc36dcd700..af8532fdc7 100644
--- a/src/mainboard/asus/f2a85-m/acpi/routing.asl
+++ b/src/mainboard/asus/f2a85-m/acpi/routing.asl
@@ -46,7 +46,7 @@
/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
-#if CONFIG_BOARD_ASUS_F2A85_M_PRO
+#if IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO)
Package(){0x000FFFFF, 0, INTA, 0 },
Package(){0x000FFFFF, 1, INTB, 0 },
Package(){0x000FFFFF, 2, INTC, 0 },
diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c
index e0a1ea4d3a..ab9e1510e7 100644
--- a/src/mainboard/asus/f2a85-m/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m/buildOpts.c
@@ -168,7 +168,7 @@
#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
-#if CONFIG_GFXUMA
+#if IS_ENABLED(CONFIG_GFXUMA)
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/