mainboard/asus: Add F2A85-M PRO variant to F2A85-M.

Status:
- The primary PCIe 16x slot works:
  It was tested with a GPU compatible with nouveau
- USB and audio are not very reliable
- The ethernet card is not seen with lspci
- The secondary pcie16x slot isn't working:
  When plugging a GPU inside, it's not seen with lspci
- SATA works: The board fully boots GNU/Linux
- Serial doesn't work
- Populating the RAM slots might have to follow
  the recommended memory configuration that is described
  in the mainboard manual in order to be able to boot.

Note that when running the shutdown command, the default
boot firmware will rewrite part of the boot flash before
powering off the machine.

Flashing coreboot internally from the default boot fimrware can
still work, if the power plug is removed after running flashrom.

Change-Id: I934de521d0acceb7770f23b2ae15c31a67ae73eb
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/16931
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

1 files changed, 133 insertions, 0 deletions

diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb
new file mode 100644
index 0000000000..d94244510c
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb
@@ -0,0 +1,133 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+chip northbridge/amd/agesa/family15tn/root_complex
+
+	device cpu_cluster 0 on
+		chip cpu/amd/agesa/family15tn
+			device lapic 10 on end
+		end
+	end
+
+	device domain 0 on
+		subsystemid 0x1022 0x1410 inherit
+		chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+
+			chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+				device pci 0.0 on  end # Root Complex
+				device pci 0.2 on  end # IOMMU
+				device pci 1.0 on  end # Internal Graphics P2P bridge 0x99XX
+				device pci 1.1 on  end # Internal Multimedia
+				device pci 2.0 on  end # PCIE SLOT0 x16 blue
+				device pci 3.0 off end # unused?
+				device pci 4.0 on  end # PCIE 4x black
+				device pci 5.0 off end # unused?
+				device pci 6.0 off end # unused?
+				device pci 7.0 off end # LAN
+				device pci 8.0 off end # NB/SB Link P2P bridge
+			end	#chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+
+			chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
+				device pci 10.0 on  end # XHCI HC0
+				device pci 10.1 on  end # XHCI HC1
+				device pci 11.0 on  end # SATA
+				device pci 12.0 on  end # USB
+				device pci 12.2 on  end # USB
+				device pci 13.0 on  end # USB
+				device pci 13.2 on  end # USB
+				device pci 14.0 on      # SMBUS
+					chip drivers/generic/generic #dimm 0
+						device i2c 50 on end # 7-bit SPD address
+					end
+					chip drivers/generic/generic #dimm 1
+						device i2c 51 on end # 7-bit SPD address
+					end
+				end # SM
+				device pci 14.1 off end # IDE	0x439c
+				device pci 14.2 on  end # HDA	0x4383
+				device pci 14.3 on      # LPC	0x439d
+					chip superio/ite/it8728f
+						register hwm_ctl_register = "0xc0"
+						register hwm_main_ctl_register = "0x33"
+						register hwm_adc_temp_chan_en_reg = "0x38"
+						register hwm_fan1_ctl_pwm = "0x00"
+						register hwm_fan2_ctl_pwm = "0x00"
+						register hwm_fan3_ctl_pwm = "0x00"
+
+						device pnp 2e.0 off #  Floppy
+							io 0x60 = 0x3f0
+							irq 0x70 = 6
+							drq 0x74 = 2
+						end
+						device pnp 2e.1 on #  Com1
+							io 0x60 = 0x3f8
+							irq 0x70 = 4
+						end
+						device pnp 2e.2 off #  Com2
+							io 0x60 = 0x2f8
+							irq 0x70 = 3
+						end
+						device pnp 2e.3 off #  Parallel Port
+							io 0x60 = 0x378
+							irq 0x70 = 7
+						end
+						device pnp 2e.4 on #  Env Controller
+							io 0x60 = 0x290
+							io 0x62 = 0x220
+							irq 0x70 = 0
+						end
+						device pnp 2e.5 on #  Keyboard
+							io 0x60 = 0x60
+							io 0x62 = 0x64
+							irq 0x70 = 1
+						end
+						device pnp 2e.6 off #  Mouse
+							irq 0x70 = 12
+						end
+						device pnp 2e.7 on #  GPIO
+							io 0x60 = 0x228 #SMI
+							io 0x62 = 0x300 #Simple I/O
+							io 0x64 = 0x238 #Phony resource IT8603E does not have it
+							irq 0x70 = 0
+						end
+						device pnp 2e.a off end #  CIR
+					end	#superio/ite/it8728f
+				end	#device pci 14.3 # LPC
+				device pci 14.4 on  end # PCI 0x4384
+				device pci 14.5 on  end # USB 2
+				device pci 14.6 off end # Gec
+				device pci 14.7 off end # SD
+				device pci 15.0 on end # PCIe 0 - onboard PCIe 1x
+				device pci 15.1 on end # PCIe 1 onboard gigabit
+				device pci 15.2 off end # unused
+				device pci 15.3 off end # unused
+
+			end	#chip southbridge/amd/agesa/hudson
+
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+			device pci 18.4 on end
+			device pci 18.5 on end
+
+			register "spdAddrLookup" = "
+			{
+				{ {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
+				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
+			}"
+
+		end	#chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+	end	#domain
+end	#chip northbridge/amd/agesa/family15tn/root_complex