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authorSven Schnelle <svens@stackframe.org>2012-07-11 21:47:11 +0200
committerPatrick Georgi <patrick@georgi-clan.de>2012-07-14 17:34:57 +0200
commit2d0d83c3dd41a95f5c27a2c7ecf0a3a8cdd5d0be (patch)
treec6b6b427c89127e7be18fce28f38abf4a9691b3d /src/mainboard/asus/dsbf/devicetree.cb
parent6fa1d3a218332230826a5a5ebd676017b30b5930 (diff)
Add ASUS DSBF mainboard
Change-Id: Iad38b92ca3a582e5aec07b92c994bfbe78b09855 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/1223 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/asus/dsbf/devicetree.cb')
-rw-r--r--src/mainboard/asus/dsbf/devicetree.cb185
1 files changed, 185 insertions, 0 deletions
diff --git a/src/mainboard/asus/dsbf/devicetree.cb b/src/mainboard/asus/dsbf/devicetree.cb
new file mode 100644
index 0000000000..b18fdaf302
--- /dev/null
+++ b/src/mainboard/asus/dsbf/devicetree.cb
@@ -0,0 +1,185 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+chip northbridge/intel/i5000
+
+ device lapic_cluster 0 on
+ chip cpu/intel/socket_LGA771
+ device lapic 0 on end
+ end
+ end
+
+ device pci_domain 0 on
+ device pci 00.0 on # Host bridge
+ subsystemid 0x1043 0x81db
+ end
+
+ device pci 02.0 on # PCI Express x8 Port 2-3
+ ioapic_irq 8 INTA 0x10
+ ioapic_irq 8 INTB 0x11
+ ioapic_irq 8 INTC 0x12
+ ioapic_irq 8 INTD 0x13
+ device pci 00.0 on # PCI Express Upstream Port
+ device pci 00.0 on # PCI Express Downstream Port E1
+ device pci 00.0 on # 6700PXH PCI Express-to-PCI Bridge A
+ ioapic_irq 8 INTA 0x11
+ ioapic_irq 8 INTB 0x10
+ ioapic_irq 8 INTC 0x11
+ ioapic_irq 8 INTD 0x10
+ # PCI slot
+ device pci 00.2 on # 6700PXH PCI Express-to-PCI Bridge B
+ # PCI slot
+ end
+ end
+ end
+ device pci 00.1 on end
+ device pci 00.3 on # PCI Express to PCI-X Bridge
+ ioapic_irq 9 INTA 3
+ ioapic_irq 9 INTB 0
+ ioapic_irq 9 INTC 1
+ ioapic_irq 9 INTD 2
+ # PCI-X Slot
+ end
+
+ end
+ end
+
+ device pci 03.0 on
+ ioapic_irq 8 INTA 0x10
+ end
+ device pci 04.0 on
+ ioapic_irq 8 INTA 0x10
+ end
+ device pci 05.0 on
+ ioapic_irq 8 INTA 0x10
+ end
+ device pci 06.0 on
+ ioapic_irq 8 INTA 0x10
+ end
+ device pci 07.0 on
+ ioapic_irq 8 INTA 0x10
+ end
+
+ device pci 10.0 on end # FBD
+ device pci 10.1 on end # FBD
+ device pci 10.2 on end # FBD
+ device pci 11.0 on end # FBD reserved
+ device pci 13.0 on end # FBD reserved
+ device pci 15.0 on end # FBD
+ device pci 16.0 on end # FBD
+
+ chip drivers/generic/ioapic
+ register "have_isa_interrupts" = "1"
+ register "irq_on_fsb" = "1"
+ register "enable_virtual_wire" = "1"
+ register "base" = "0xfec00000"
+ device ioapic 8 on end
+ end
+
+ chip drivers/generic/ioapic
+ register "irq_on_fsb" = "1"
+ register "base" = "0xfec80000"
+ device ioapic 9 on end
+ end
+
+ chip southbridge/intel/i3100
+ register "pirq_a_d" = "0x0b0b0b0b"
+ register "pirq_e_h" = "0x80808080"
+ register "sata_ports_implemented" = "0x3f"
+
+ device pci 1c.0 on
+ ioapic_irq 8 INTA 0x14
+ ioapic_irq 8 INTB 0x15
+ ioapic_irq 8 INTC 0x16
+ ioapic_irq 8 INTD 0x17
+ end # PCIe bridge
+ device pci 1d.0 on
+ ioapic_irq 8 INTA 0x10
+ end # USB UHCI
+ device pci 1d.1 on
+ ioapic_irq 8 INTB 0x11
+ end # USB UHCI
+ device pci 1d.2 on
+ ioapic_irq 8 INTC 0x12
+ end # USB UHCI
+ device pci 1d.3 on
+ ioapic_irq 8 INTD 0x13
+ end # USB UHCI
+ device pci 1d.7 on end # USB2 EHCI
+ device pci 1e.0 on
+ device pci 01.0 on end
+ end
+
+ device pci 1f.0 on # PCI-LPC bridge
+ ioapic_irq 8 INTA 0x11
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off end # FDC
+ device pnp 2e.1 on # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Serial Port 1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+
+ device pnp 2e.3 off end
+ device pnp 2e.5 on # KBC
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # Game port / MIDI
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 on end # GPIO3
+ device pnp 2e.a on end # ACPI
+ device pnp 2e.b off end # HWMON
+ end
+ end
+ device pci 1f.1 off end # IDE
+ device pci 1f.2 on end # SATA
+ device pci 1f.3 on # SMBUS
+ chip drivers/i2c/w83793
+ register "mfc" = "0x28"
+ register "fanin" = "0x1f"
+ register "peci_agent_conf" = "0x33"
+ register "tcase0" = "0x5e"
+ register "tcase1" = "0x5e"
+ register "tcase2" = "0x5e"
+ register "tcase3" = "0x5e"
+ register "tr_enable" = "0x01"
+ register "critical_temperature" = "0x7f"
+ register "td1_fan_select" = "0x09"
+ register "td2_fan_select" = "0x09"
+ register "td3_fan_select" = "0x09"
+ register "td4_fan_select" = "0x09"
+ register "tr1_fan_select" = "0x09"
+ register "tr2_fan_select" = "0x09"
+ device i2c 0x2f on end
+ end
+ end
+ end
+ end
+end