diff options
| author | Mike Banon <mikebdp2@gmail.com> | 2020-01-07 18:47:40 +0300 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-01-10 15:18:28 +0000 |
| commit | 834d8c29988f545bccedbd6af0ceaac593421077 (patch) | |
| tree | 75902f58bffa1d09ab8454f2aab23c1d92f9c38f /src/mainboard/asus/am1i-a/irq_tables.c | |
| parent | b8de01583531a758eb87c910417e2dfb89975ac2 (diff) | |
asus/am1i-a: fix the blue "USB 3.0" ports for OHCI/EHCI "USB 2.0" mode
Set up the proper IRQ routing for OHCI/EHCI devices which appear if
XHCI controller is disabled (CONFIG_HUDSON_XHCI_ENABLE is not set).
Now both "USB 3.0" ports are working fine at OHCI/EHCI "USB 2.0" mode.
They also work fine if XHCI controller is enabled.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I50a773eeab890627abc963e0a61f781d1cea3259
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Diffstat (limited to 'src/mainboard/asus/am1i-a/irq_tables.c')
| -rw-r--r-- | src/mainboard/asus/am1i-a/irq_tables.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/asus/am1i-a/irq_tables.c b/src/mainboard/asus/am1i-a/irq_tables.c index c8ccbeb231..84110d1882 100644 --- a/src/mainboard/asus/am1i-a/irq_tables.c +++ b/src/mainboard/asus/am1i-a/irq_tables.c @@ -26,7 +26,7 @@ const struct irq_routing_table intel_irq_routing_table = { 0x439d, /* Device */ 0, /* Miniport */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xa8, /* Checksum (has to be set to some value that + 0x3b, /* Checksum (has to be set to some value that * would give 0 after the sum of all bytes * for this structure (including checksum). */ @@ -39,6 +39,7 @@ const struct irq_routing_table intel_irq_routing_table = { {0x00, (0x12 << 3) | 0x0, {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, {0x00, (0x13 << 3) | 0x0, {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, {0x00, (0x14 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0}, + {0x00, (0x16 << 3) | 0x0, {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, {0x01, (0x00 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0}, {0x02, (0x00 << 3) | 0x0, {{0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, } |