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authorIonela Voinescu <ionela.voinescu@imgtec.com>2014-12-01 18:31:48 +0000
committerPatrick Georgi <pgeorgi@google.com>2015-04-13 20:25:21 +0200
commit8fa8f4bdc341d3249aec5fda87f80417cb8917b3 (patch)
treeffd3e852235ffaa45587a36a3bbd57c3b8088dee /src/mainboard/asus/a8v-e_se
parent49efaf260f2289322110dcf21900146046439d37 (diff)
arch/mips: provide proper cache primitives
This provides the opportunity to remove the kludge of disabling caches altogether in the bootblock. [pg: originally, this commit also provided automatic cache management after loading stages, ie. flush dcache, so code ends up in icache. This is done differently in upstream, so it's left out here] BUG=chrome-os-partner:34127, chrome-os-partner:31438 TEST=with this fix romstage, ramstage and payload are executed properly BRANCH=none Change-Id: I568c68d02b2cd9c1c2c9c1495ba3343c82509ccc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 95ab0f159cabf21fc100f371d451211e7d113761 Original-Change-Id: Iaf90b052073dd355ab9114e8dba9f5ef76188c94 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/232410 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9618 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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