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authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-05-24 00:04:22 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2018-05-31 03:41:11 +0000
commit1740230ace3aeede3a7ee5cadd1e17744cda07b3 (patch)
treebf4e9f45d71fef44056ba901ac91fcbfb423a525 /src/mainboard/asus/a8n_e
parentf054a4bf3d6ce459d15c9375e4ca2390d04ffb68 (diff)
Remove all AMD K8 boards
Platforms with LATE_CBMEM_INIT were agreed to be removed with 4.7 release late 2017. Change-Id: I0ecbb40f8c7ebdf68217f50af5624905d9005c64 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/asus/a8n_e')
-rw-r--r--src/mainboard/asus/a8n_e/Kconfig62
-rw-r--r--src/mainboard/asus/a8n_e/Kconfig.name2
-rw-r--r--src/mainboard/asus/a8n_e/acpi_tables.c71
-rw-r--r--src/mainboard/asus/a8n_e/board_info.txt7
-rw-r--r--src/mainboard/asus/a8n_e/cmos.default11
-rw-r--r--src/mainboard/asus/a8n_e/cmos.layout56
-rw-r--r--src/mainboard/asus/a8n_e/devicetree.cb121
-rw-r--r--src/mainboard/asus/a8n_e/dsdt.asl265
-rw-r--r--src/mainboard/asus/a8n_e/get_bus_conf.c116
-rw-r--r--src/mainboard/asus/a8n_e/irq_tables.c193
-rw-r--r--src/mainboard/asus/a8n_e/mptable.c123
-rw-r--r--src/mainboard/asus/a8n_e/romstage.c150
12 files changed, 0 insertions, 1177 deletions
diff --git a/src/mainboard/asus/a8n_e/Kconfig b/src/mainboard/asus/a8n_e/Kconfig
deleted file mode 100644
index 1852ae45e0..0000000000
--- a/src/mainboard/asus/a8n_e/Kconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-if BOARD_ASUS_A8N_E || BOARD_ASUS_A8N_SLI
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_939
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_NVIDIA_CK804
- select HT_CHAIN_DISTRIBUTE
- select SUPERIO_ITE_IT8712F
- select HAVE_OPTION_TABLE
- select HAVE_CMOS_DEFAULT
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select BOARD_ROMSIZE_KB_512
- select CK804_USE_NIC
- select CK804_USE_ACI
- select QRANK_DIMM_SUPPORT
- select HAVE_ACPI_TABLES
-
-config MAINBOARD_DIR
- string
- default asus/a8n_e
-
-config DCACHE_RAM_BASE
- hex
- default 0xcf000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x01000
-
-config APIC_ID_OFFSET
- hex
- default 0x0
-
-if BOARD_ASUS_A8N_E
-config MAINBOARD_PART_NUMBER
- string
- default "A8N-E"
-endif
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config IRQ_SLOT_COUNT
- int
- default 13
-
-endif # BOARD_ASUS_A8N_E
diff --git a/src/mainboard/asus/a8n_e/Kconfig.name b/src/mainboard/asus/a8n_e/Kconfig.name
deleted file mode 100644
index 02b00e7dd8..0000000000
--- a/src/mainboard/asus/a8n_e/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASUS_A8N_E
- bool "A8N-E"
diff --git a/src/mainboard/asus/a8n_e/acpi_tables.c b/src/mainboard/asus/a8n_e/acpi_tables.c
deleted file mode 100644
index da90fd3ddf..0000000000
--- a/src/mainboard/asus/a8n_e/acpi_tables.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * ACPI support
- * written by Stefan Reinauer <stepan@openbios.org>
- * (C) 2005 Stefan Reinauer
- *
- * Copyright 2005 AMD
- * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include "../../../northbridge/amd/amdk8/acpi.h"
-
-/* APIC */
-unsigned long acpi_fill_madt(unsigned long current)
-{
- struct device *dev;
- struct resource *res;
-
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /* Write NVIDIA CK804 IOAPIC. */
- dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0));
- ASSERT(dev != NULL);
-
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- ASSERT(res != NULL);
-
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
- CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS, res->base, 0);
-
- /* Initialize interrupt mapping if mptable.c didn't. */
-#if (!CONFIG_GENERATE_MP_TABLE)
-#error untested config
- pci_write_config32(dev, 0x7c, 0x0120d218);
- pci_write_config32(dev, 0x80, 0x12008a00);
- pci_write_config32(dev, 0x84, 0x0000007d);
-#endif
-
- /* IRQ of timer */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- /* IRQ9 */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
-
- /* create all subtables for processors */
- /* acpi_create_madt_lapic_nmis returns current, not size. */
- current = acpi_create_madt_lapic_nmis(current,
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
-
- return current;
-}
diff --git a/src/mainboard/asus/a8n_e/board_info.txt b/src/mainboard/asus/a8n_e/board_info.txt
deleted file mode 100644
index 2e3e6424e0..0000000000
--- a/src/mainboard/asus/a8n_e/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Category: desktop
-Board URL: http://www.asus.com/Motherboards/AMD_Socket_939/A8NE/
-ROM package: PLCC
-ROM protocol: LPC
-ROM socketed: y
-Flashrom support: y
-Release year: 2005
diff --git a/src/mainboard/asus/a8n_e/cmos.default b/src/mainboard/asus/a8n_e/cmos.default
deleted file mode 100644
index 84dd0274af..0000000000
--- a/src/mainboard/asus/a8n_e/cmos.default
+++ /dev/null
@@ -1,11 +0,0 @@
-boot_option=Fallback
-debug_level=Spew
-power_on_after_fail=Enable
-ECC_memory=Disable
-hw_scrubber=Enable
-interleave_chip_selects=Enable
-max_mem_clock=DDR400
-multi_core=Enable
-slow_cpu=off
-nmi=Enable
-iommu=Enable
diff --git a/src/mainboard/asus/a8n_e/cmos.layout b/src/mainboard/asus/a8n_e/cmos.layout
deleted file mode 100644
index dc2977b250..0000000000
--- a/src/mainboard/asus/a8n_e/cmos.layout
+++ /dev/null
@@ -1,56 +0,0 @@
-entries
- 0 384 r 0 reserved_memory
- 384 1 e 4 boot_option
- 386 1 e 1 ECC_memory
- 388 4 h 0 reboot_counter
-# 392 3 r 0 unused
- 395 1 e 1 hw_scrubber
- 396 1 e 1 interleave_chip_selects
- 397 2 e 8 max_mem_clock
- 399 1 e 2 multi_core
- 400 1 e 1 power_on_after_fail
- 412 4 e 6 debug_level
- 440 4 e 9 slow_cpu
- 444 1 e 1 nmi
- 445 1 e 1 iommu
- 728 256 h 0 user_data
- 984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
- 1000 24 r 0 reserved_memory1
-
-enumerations
-
-#ID value text
- 1 0 Disable
- 1 1 Enable
- 2 0 Enable
- 2 1 Disable
- 4 0 Fallback
- 4 1 Normal
-
- 6 5 Notice
- 6 6 Info
- 6 7 Debug
- 6 8 Spew
- 7 0 Network
- 7 1 HDD
- 7 2 Floppy
- 7 8 Fallback_Network
- 7 9 Fallback_HDD
- 7 10 Fallback_Floppy
- 8 0 DDR400
- 8 1 DDR333
- 8 2 DDR266
- 8 3 DDR200
- 9 0 off
- 9 1 87.5 %
- 9 2 75.0 %
- 9 3 62.5 %
- 9 4 50.0 %
- 9 5 37.5 %
- 9 6 25.0 %
- 9 7 12.5 %
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asus/a8n_e/devicetree.cb b/src/mainboard/asus/a8n_e/devicetree.cb
deleted file mode 100644
index bbbfeb89f2..0000000000
--- a/src/mainboard/asus/a8n_e/devicetree.cb
+++ /dev/null
@@ -1,121 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/amd/socket_939 # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
- end
-
- device domain 0 on # PCI domain
- subsystemid 0x1043 0x815a inherit
- chip northbridge/amd/amdk8 # Northbridge / RAM controller
- device pci 18.0 on # Link 0 == LDT 0
- chip southbridge/nvidia/ck804 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/ite/it8712f # Super I/O
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.2 off # Com2 (N/A on this board)
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.3 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 3
- end
- device pnp 2e.4 on # Environment controller
- io 0x60 = 0x290
- io 0x62 = 0x0000
- irq 0x70 = 0x00
- end
- device pnp 2e.5 on # PS/2 keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x71 = 2
- end
- device pnp 2e.6 on # PS/2 mouse
- irq 0x70 = 12
- irq 0x71 = 2
- end
- device pnp 2e.7 on # GPIO config
- io 0x60 = 0x0800
- io 0x62 = 0x0808
- io 0x64 = 0x0810
- # Set GPIO 1 & 2
- io 0x25 = 0x0000
- # Set GPIO 3 & 4
- io 0x27 = 0x2540
- # GPIO Polarity for Set 3
- io 0xb2 = 0x2100
- # GPIO Pin Internal Pull up for Set 3
- io 0xba = 0x0100
- # Simple I/O register config
- io 0xc0 = 0x0000
- io 0xc2 = 0x2540
- io 0xc8 = 0x0000
- io 0xca = 0x0500
- end
- device pnp 2e.8 on # MIDI port
- io 0x60 = 0x300
- irq 0x70 = 10
- end
- device pnp 2e.9 on # Game port
- io 0x60 = 0x201
- end
- device pnp 2e.a off # IR (N/A on this board)
- io 0x60 = 0x310
- irq 0x70 = 11
- end
- end
- end
- device pci 1.1 on # SM 0
- # chip drivers/generic/generic # DIMM 0-0-0
- # device i2c 50 on end
- # end
- # chip drivers/generic/generic # DIMM 0-0-1
- # device i2c 51 on end
- # end
- # chip drivers/generic/generic # DIMM 0-1-0
- # device i2c 52 on end
- # end
- # chip drivers/generic/generic # DIMM 0-1-1
- # device i2c 53 on end
- # end
- end
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 on end # Onboard audio (ACI)
- device pci 4.1 off end # Onboard modem (MCI), N/A
- device pci 6.0 on end # IDE
- device pci 7.0 on end # SATA 1
- device pci 8.0 on end # SATA 0
- device pci 9.0 on end # PCI
- device pci a.0 on end # NIC
- device pci b.0 on end # PCI E 3
- device pci c.0 on end # PCI E 2
- device pci d.0 on end # PCI E 1
- device pci e.0 on end # PCI E 0
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- # TODO
- # register "mac_eeprom_smbus" = "3"
- # register "mac_eeprom_addr" = "0x51"
- end
- end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/asus/a8n_e/dsdt.asl b/src/mainboard/asus/a8n_e/dsdt.asl
deleted file mode 100644
index 45aeaf1c21..0000000000
--- a/src/mainboard/asus/a8n_e/dsdt.asl
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- */
-
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1)
-{
- #include "northbridge/amd/amdk8/util.asl"
-
- /* For now only define 2 power states:
- * - S0 which is fully on
- * - S5 which is soft off
- * Any others would involve declaring the wake up methods.
- */
- Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
- Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 })
-
- Name (PICM, 0x00)
- Method (_PIC, 1, Serialized) {
- Store (Arg0, PICM)
- }
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Top PCI device (CK804) */
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x00)
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0CF8, // Address Length
- ,, , TypeStatic)
- })
- /* Methods bellow use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- \_SB.GXXX(node, link)
- */
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
-#include "southbridge/nvidia/ck804/acpi/ck804.asl"
-
- /* PCI Routing Table */
- Name (_PRT, Package () {
- Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LLAS, 0x00 },//APCS
- Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LLAS, 0x00 },//APCS
- Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LUOH, 0x00 },//APCF
- Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LUEH, 0x00 },//APCL
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LAUD, 0x00 },//APCJ
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LMOD, 0x00 },//APCK
- Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LPA0, 0x00 },//APCZ
- Package (0x04) { 0x0007FFFF, 0x00, \_SB.PCI0.LSA0, 0x00 },//APSI
- Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LSA1, 0x00 },//APSJ
-
- Package (0x04) { 0x0009FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0009FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0009FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0009FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
-
- Package (0x04) { 0x000AFFFF, 0x00, \_SB.PCI0.LEMA, 0x00 },//APCH
-
- Package (0x04) { 0x000BFFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//APC2
- Package (0x04) { 0x000BFFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },//APC3
- Package (0x04) { 0x000BFFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },//APC4
- Package (0x04) { 0x000BFFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },//APC1
-
- Package (0x04) { 0x000CFFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//APC1
- Package (0x04) { 0x000CFFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },//APC2
- Package (0x04) { 0x000CFFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },//APC3
- Package (0x04) { 0x000CFFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },//APC4
-
- Package (0x04) { 0x000DFFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },//APC4
- Package (0x04) { 0x000DFFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },//APC1
- Package (0x04) { 0x000DFFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },//APC2
- Package (0x04) { 0x000DFFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },//APC3
-
- Package (0x04) { 0x000EFFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//APC3
- Package (0x04) { 0x000EFFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },//APC4
- Package (0x04) { 0x000EFFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },//APC1
- Package (0x04) { 0x000EFFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },//APC2
- })
-
- Device (PCIC)
- {
- Name (_ADR, 0x00090000)
- Name (_UID, 0x00)
- Name (_PRT, Package () {
- /* AGR slot */
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
- })
- }
-
- /* 2:00 PCIe x1 */
- Device (PEX1)
- {
- Name (_ADR, 0x000d0000)
- Name (_UID, 0x00)
- }
-
- /* 3:00 PCIe x16 */
- Device (PEX0)
- {
- Name (_ADR, 0x000e0000)
- Name (_UID, 0x00)
- }
-
- Device (LPC) {
- Name (_HID, EisaId ("PNP0A05"))
- Name (_ADR, 0x00010000)
-
- OperationRegion (CF44, PCI_Config, 0x44, 0x04)
- Field (CF44, ByteAcc, NoLock, Preserve)
- {
- ETBA, 32,
- }
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IRQNoFlags () {12}
- })
- Return (TMP)
- }
- }
-
- /* Parallel port */
- Device (LP0)
- {
- Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- FixedIO (0x0378, 0x10)
- IRQNoFlags () {7}
- })
- Return (TMP)
- }
- }
-
- /* Floppy controller */
- Device (FDC0)
- {
- Name (_HID, EisaId ("PNP0700"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () {
- FixedIO (0x03F0, 0x08)
- IRQNoFlags () {6}
- DMA (Compatibility, NotBusMaster, Transfer8) {2}
- })
- Return (BUF0)
- }
- }
-#if 0
- Device (HPET)
- {
- Name (_HID, EisaId ("PNP0103"))
- Name (CRS, ResourceTemplate ()
- {
- Memory32Fixed (ReadOnly,
- 0x00000000,
- 0x00001000,
- _Y02)
- })
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0F)
- }
- Method (_CRS, 0, NotSerialized)
- {
- CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._BAS, HPT)
- Store (ETBA, HPT)
- Return (CRS)
- }
-
- }
-#endif
- }
- }
- }
-}
diff --git a/src/mainboard/asus/a8n_e/get_bus_conf.c b/src/mainboard/asus/a8n_e/get_bus_conf.c
deleted file mode 100644
index b1e94d8896..0000000000
--- a/src/mainboard/asus/a8n_e/get_bus_conf.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/multicore.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include <stdlib.h>
-
-/*
- * Global variables for MB layouts and these will be shared by irqtable,
- * mptable and acpi_tables.
- */
-/* busnum is default */
-unsigned char bus_ck804[6];
-unsigned apicid_ck804;
-
-/*
- * Here you only need to set value in pci1234 for HT-IO that could be installed
- * or not. You may need to preset pci1234 for HT-IO board, please refer to
- * src/northbridge/amd/amdk8/get_sblk_pci1234.c for details.
- */
-unsigned pci1234x[] = {
- 0x0000ff0, /* No HTIO for A8N-E */
-};
-
-/*
- * HT Chain device num, actually it is unit id base of every ht device in
- * chain, assume every chain only have 4 ht device at most.
- */
-unsigned hcdnx[] = {
- 0x20202020, /* A8N-E has only one ht-chain */
-};
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
- unsigned apicid_base, sbdn;
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; /* Do it only once. */
-
- get_bus_conf_done = 1;
-
- /* FIXME: Is this really needed twice? */
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
- sbdn = sysconf.sbdn;
-
- for (i = 0; i < 6; i++)
- bus_ck804[i] = 0;
-
- bus_ck804[0] = (sysconf.pci1234[0] >> 16) & 0xff;
-
- /* CK804 */
- dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x09, 0));
- if (dev) {
- bus_ck804[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_ck804[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804[2]++;
- } else {
- printk
- (BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x09);
- bus_ck804[1] = 2;
- bus_ck804[2] = 3;
- }
-
- for (i = 2; i < 6; i++) {
- dev = dev_find_slot(bus_ck804[0],
- PCI_DEVFN(sbdn + 0x0b + i - 2, 0));
- if (dev) {
- bus_ck804[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- bus_ck804[0], sbdn + 0x0b + i - 2);
- }
- }
-
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(3);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- apicid_ck804 = apicid_base + 0;
-}
diff --git a/src/mainboard/asus/a8n_e/irq_tables.c b/src/mainboard/asus/a8n_e/irq_tables.c
deleted file mode 100644
index 59d506df01..0000000000
--- a/src/mainboard/asus/a8n_e/irq_tables.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern unsigned char bus_isa;
-extern unsigned char bus_ck804[6];
-
-
-/**
- * Add one line to IRQ table.
- */
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-/**
- * Create the IRQ routing table.
- * Values are derived from getpir generated code.
- */
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num, sbdn;
- uint8_t *v, sum = 0;
- int i;
-
- /* get_bus_conf() will find out all bus num and APIC that share with
- * mptable.c and mptable.c.
- */
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000. */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *)(addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
- pirq->rtr_bus = bus_ck804[0];
- pirq->rtr_devfn = ((sbdn + 9) << 3) | 0;
- pirq->exclusive_irqs = 0x828;
- pirq->rtr_vendor = 0x10de;
- pirq->rtr_device = 0x005c;
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-
- /* Slot1 PCIE 16x */
- write_pirq_info(pirq_info, bus_ck804[1], (0 << 3) | 0, 0x3, 0xdeb8, 0x4,
- 0xdeb8, 0x1, 0xdeb8, 0x2, 0xdeb8, 4, 0);
- pirq_info++;
- slot_num++;
-
- /* Slot2 PCIE 1x */
- write_pirq_info(pirq_info, bus_ck804[2], (0 << 3) | 0, 0x4, 0xdeb8, 0x1,
- 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 5, 0);
- pirq_info++;
- slot_num++;
-
- /* Slot3 PCIE 1x */
- write_pirq_info(pirq_info, bus_ck804[3], (0 << 3) | 0, 0x1, 0xdeb8, 0x2,
- 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 6, 0);
- pirq_info++;
- slot_num++;
-
- /* Slot4 PCIE 4x */
- write_pirq_info(pirq_info, bus_ck804[4], (0x4 << 3) | 0, 0x2,
- 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, 7, 0);
- pirq_info++;
- slot_num++;
-
- /* Slot5 - Slot7 PCI */
- for (i = 0; i < 3; i++) {
- write_pirq_info(pirq_info, bus_ck804[5], (0 << (6 + i)) | 0,
- ((i + 0) % 4) + 1, 0xdeb8,
- ((i + 1) % 4) + 1, 0xdeb8,
- ((i + 2) % 4) + 1, 0xdeb8,
- ((i + 3) % 4) + 1, 0xdeb8, i, 0);
- pirq_info++;
- slot_num++;
- }
-
- /* PCI bridge */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 9) << 3) | 0, 0x1,
- 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* SMBus */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 1) << 3) | 0, 0x2,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* USB */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 2) << 3) | 0, 0x1,
- 0xdeb8, 0x2, 0xdeb8, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* Audio */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 4) << 3) | 0, 0x1,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* SATA */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 7) << 3) | 0, 0x1,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* SATA */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 8) << 3) | 0, 0x1,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* NIC */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 0xa) << 3) | 0, 0x1,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
-#if 0
- /* Firewire? */
- write_pirq_info(pirq_info, bus_ck804_1, (0x5 << 3) | 0, 0x3, 0xdeb8, 0,
- 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-#endif
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
- if (sum != pirq->checksum)
- pirq->checksum = sum;
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/asus/a8n_e/mptable.c b/src/mainboard/asus/a8n_e/mptable.c
deleted file mode 100644
index 40a06a4c77..0000000000
--- a/src/mainboard/asus/a8n_e/mptable.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern unsigned char bus_ck804[6];
-extern unsigned apicid_ck804;
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- unsigned sbdn;
- int bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- {
- struct device *dev;
- struct resource *res;
- uint32_t dword;
-
- dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- smp_write_ioapic(mc, apicid_ck804, 0x11,
- res2mmio(res, 0, 0));
- }
-
- /* Initialize interrupt mapping. */
- dword = 0x01200000;
- pci_write_config32(dev, 0x7c, dword);
-
- dword = 0x12008009;
- pci_write_config32(dev, 0x80, dword);
-
- dword = 0x0002010d;
- pci_write_config32(dev, 0x84, dword);
-
- }
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0);
-
- // Onboard ck804 smbus
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 1) << 2) | 1, apicid_ck804,
- 0xa);
-
- // Onboard ck804 USB 1.1
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804,
- 0x15);
-
- // Onboard ck804 USB 2
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804,
- 0x14);
-
- /* Onboard audio */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 4) << 2) | 0, apicid_ck804, 0x3);
-
- // Onboard ck804 SATA 0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804,
- 0x17);
-
- // Onboard ck804 SATA 1
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804,
- 0x16);
-
- // Onboard ck804 NIC
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 10) << 2) | 0, apicid_ck804,
- 0x17);
-
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, bus_ck804[0]);
-
- /* There is no extension information... */
-
- /* Compute the checksums. */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c
deleted file mode 100644
index e4ed339924..0000000000
--- a/src/mainboard/asus/a8n_e/romstage.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* Used by ite_enable_serial(). */
-#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
-#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO)
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <cpu/x86/lapic.h>
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8712f/it8712f.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <console/console.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include <southbridge/nvidia/ck804/early_smbus.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include <spd.h>
-#include <northbridge/amd/amdk8/pre_f.h>
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned int device, unsigned int address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "lib/generic_sdram.c"
-#include <southbridge/nvidia/ck804/early_setup_ss.h>
-#include "southbridge/nvidia/ck804/early_setup.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-static void sio_setup(void)
-{
- uint32_t dword;
- uint8_t byte;
-
- /* Subject decoding */
- byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, byte);
-
- /* LPC Positive Decode 0 */
- dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0);
- dword |= (1 << 0) | (1 << 1); /* Serial 0, Serial 1 */
- pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr[] = {
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
-#endif
- };
-
- int needs_reset;
- unsigned nodes, bsp_apicid = 0;
- struct mem_controller ctrl[8];
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- sio_setup();
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx);
-
- ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
-#if 0
- dump_pci_device(PCI_DEV(0, 0x18, 0));
-#endif
-
- needs_reset = setup_coherent_ht_domain();
-
- wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /* It is said that we should start core1 after all core0 launched. */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- needs_reset |= ht_setup_chains_x();
- needs_reset |= ck804_early_setup_x();
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-
- allow_all_aps_stop(bsp_apicid);
-
- nodes = get_nodes();
- /* It's the time to set ctrl now. */
- fill_mem_ctrl(nodes, ctrl, spd_addr);
-
- enable_smbus();
-
-#if 0
- dump_spd_registers(&ctrl[0]);
- dump_smbus_registers();
-#endif
-
- sdram_initialize(nodes, ctrl);
-
-#if 0
- print_pci_devices();
- dump_pci_devices();
-#endif
-}