diff options
author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-02-07 21:43:48 +0000 |
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committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-02-07 21:43:48 +0000 |
commit | abf2ad716daff751d75907d47bcae4a7044fd7b4 (patch) | |
tree | f82427b43d76a4791253373affed1af8669e2e7b /src/mainboard/asus/a8n_e | |
parent | 389240f288b2708617a35ebe8d7f89b3bff316c5 (diff) |
newconfig is no more.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/asus/a8n_e')
-rw-r--r-- | src/mainboard/asus/a8n_e/Config.lb | 241 | ||||
-rw-r--r-- | src/mainboard/asus/a8n_e/Options.lb | 168 |
2 files changed, 0 insertions, 409 deletions
diff --git a/src/mainboard/asus/a8n_e/Config.lb b/src/mainboard/asus/a8n_e/Config.lb deleted file mode 100644 index 374629c5b3..0000000000 --- a/src/mainboard/asus/a8n_e/Config.lb +++ /dev/null @@ -1,241 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## (Written by Yinghai Lu <yinghailu@amd.com> for AMD) -## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de> -## (Thanks to LSRA University of Mannheim for their support) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb - -arch i386 end -driver mainboard.o -# Needed by irq_tables and mptable and acpi_tables. -object get_bus_conf.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - if CONFIG_USE_INIT - makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - else - makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - end -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -end -mainboardinit cpu/x86/32bit/entry32.inc - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - ldscript /cpu/amd/car/cache_as_ram.lds - end -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -end -# Include an ID string (for safe flashing). -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -# ROMSTRAP table for CK804. -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit southbridge/nvidia/ck804/romstrap.inc - ldscript /southbridge/nvidia/ck804/romstrap.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit southbridge/nvidia/ck804/romstrap.inc - ldscript /southbridge/nvidia/ck804/romstrap.lds - end -end - mainboardinit cpu/amd/car/cache_as_ram.inc -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - ldscript /arch/i386/lib/failover_failover.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - end -end - if CONFIG_USE_INIT - initobject auto.o - else - mainboardinit ./auto.inc - end -config chip.h - -chip northbridge/amd/amdk8/root_complex # Root complex - device apic_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # Socket 939 CPU - device apic 0 on end # APIC - end - end - - device pci_domain 0 on # PCI domain - chip northbridge/amd/amdk8 # mc0 - device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/ite/it8712f # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.4 on # Environment controller - io 0x60 = 0x290 - io 0x62 = 0x0000 - irq 0x70 = 0x00 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x71 = 2 - end - device pnp 2e.6 on # PS/2 mouse - irq 0x70 = 12 - irq 0x71 = 2 - end - device pnp 2e.7 on # GPIO config - io 0x60 = 0x0800 - # Set GPIO 1 & 2 - io 0x25 = 0x0000 - # Set GPIO 3 & 4 - io 0x27 = 0x2540 - # GPIO Polarity for Set 3 - io 0xb2 = 0x2100 - # GPIO Pin Internal Pull up for Set 3 - io 0xba = 0x0100 - # Simple I/O register config - io 0xc0 = 0x0000 - io 0xc2 = 0x2540 - io 0xc8 = 0x0000 - io 0xca = 0x0500 - end - device pnp 2e.8 on # Midi port - io 0x60 = 0x300 - irq 0x70 = 10 - end - device pnp 2e.9 on # Game port - io 0x60 = 0x201 - end - device pnp 2e.a off # IR (N/A on this board) - io 0x60 = 0x310 - irq 0x70 = 11 - end - end - end - device pci 1.1 on # SM 0 - # chip drivers/generic/generic #dimm 0-0-0 - # device i2c 50 on end - # end - # chip drivers/generic/generic #dimm 0-0-1 - # device i2c 51 on end - # end - # chip drivers/generic/generic #dimm 0-1-0 - # device i2c 52 on end - # end - # chip drivers/generic/generic #dimm 0-1-1 - # device i2c 53 on end - # end - # chip drivers/generic/generic #dimm 1-0-0 - # device i2c 54 on end - # end - # chip drivers/generic/generic #dimm 1-0-1 - # device i2c 55 on end - # end - # chip drivers/generic/generic #dimm 1-1-0 - # device i2c 56 on end - # end - # chip drivers/generic/generic #dimm 1-1-1 - # device i2c 57 on end - # end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # Onboard audio (ACI) - device pci 4.1 off end # Onboard modem (MCI), N/A - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on end # PCI - device pci a.0 on end # NIC - device pci b.0 on end # PCI E 3 - device pci c.0 on end # PCI E 2 - device pci d.0 on end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # register "mac_eeprom_smbus" = "3" - # register "mac_eeprom_addr" = "0x51" - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end -end diff --git a/src/mainboard/asus/a8n_e/Options.lb b/src/mainboard/asus/a8n_e/Options.lb deleted file mode 100644 index a03db4bb0b..0000000000 --- a/src/mainboard/asus/a8n_e/Options.lb +++ /dev/null @@ -1,168 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de> -## (Thanks to LSRA University of Mannheim for their support) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_USE_FAILOVER_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_FAILOVER_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_FAILOVER_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_CONSOLE_BTEXT -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_AP_CODE_IN_CAR -uses CONFIG_MEM_TRAIN_SEQ -uses CONFIG_WAIT_BEFORE_CPUS_INIT -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID -uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_ID_SECTION_OFFSET - -default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 - CONFIG_FAILOVER_SIZE -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_FAILOVER_SIZE = 4 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_HAVE_FAILOVER_BOOT = 1 -default CONFIG_HAVE_HARD_RESET = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 13 -default CONFIG_GENERATE_MP_TABLE = 1 -default CONFIG_HAVE_OPTION_TABLE = 1 -# Move the default coreboot CMOS range off of AMD RTC registers. -default CONFIG_LB_CKS_RANGE_START = 49 -default CONFIG_LB_CKS_RANGE_END = 122 -default CONFIG_LB_CKS_LOC = 123 -# SMP support (only worry about 2 micro processors). -default CONFIG_SMP = 1 -default CONFIG_MAX_CPUS = 2 -default CONFIG_MAX_PHYSICAL_CPUS = 1 -default CONFIG_LOGICAL_CPUS = 1 -# 1G memory hole. -default CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -# HT Unit ID offset, default is 1, the typical one. -default CONFIG_HT_CHAIN_UNITID_BASE = 0 -# Real SB Unit ID, default is 0x20, mean don't touch it at last. -# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x10 -# Make the SB HT chain on bus 0, default is not (0). -default CONFIG_SB_HT_CHAIN_ON_BUS0 = 2 -# Only offset for SB chain?, default is yes(1). -default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 -# default CONFIG_CONSOLE_BTEXT = 1 # BTEXT console -default CONFIG_CONSOLE_VGA = 1 # For VGA console -default CONFIG_PCI_ROM_RUN = 1 # For VGA console -default CONFIG_USE_DCACHE_RAM = 1 -default CONFIG_DCACHE_RAM_BASE = 0xc8000 -default CONFIG_DCACHE_RAM_SIZE = 32 * 1024 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 4 * 1024 -default CONFIG_USE_INIT = 0 -default CONFIG_AP_CODE_IN_CAR = 0 -default CONFIG_MEM_TRAIN_SEQ = 2 -default CONFIG_WAIT_BEFORE_CPUS_INIT = 0 -# default CONFIG_ENABLE_APIC_EXT_ID = 0 -# default CONFIG_APIC_ID_OFFSET = 0x10 -# default CONFIG_LIFT_BSP_APIC_ID = 0 -# default CONFIG_PCI_64BIT_PREF_MEM = 1 -default CONFIG_IOAPIC = 1 -default CONFIG_MAINBOARD_PART_NUMBER = "A8N-E" -default CONFIG_MAINBOARD_VENDOR = "ASUS" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -# Only use the option table in a normal image. -default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE) -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_GDB_STUB = 0 -default CONFIG_USE_PRINTK_IN_CAR=1 -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8 -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" -default CONFIG_ID_SECTION_OFFSET = 0x80 - -end |