diff options
author | Balazs Vinarz <vinibali1@gmail.com> | 2019-01-18 10:53:13 +0100 |
---|---|---|
committer | Angel Pons <th3fanbus@gmail.com> | 2020-08-13 17:34:04 +0000 |
commit | ffa710b9dd241cc7545858a2ac69f7cdb214cddf (patch) | |
tree | 270c3262c06d9bf4280f46081d343a8e14e548b4 /src/mainboard/asus/a88xm-e/dsdt.asl | |
parent | 414d7e4642991696dc81fbcb7ac68fe75fa4bc12 (diff) |
mb/asus: Add Asus A88XM-E FM2+ with documentation
The port is based on the F2A85-M, the main differences are:
- 2 DDR3 dimms
- 2 PS/2 ports
- 2*USB2.0 and 2*USB3.0 ports
- 3+2 phase VRM
- 6 channel audio
- 6 SATA ports
- ASP1206 VRM controller
- Bolton D4 chipset
- no optical SPDIF/IO
Successfully booted configurations:
-RAM: 2*8GB Kingston KVR 1333Mhz LP, 2*8GB Crucial BLT8G3D1869DT1TX0
-CPU: AMD A8-6500 (Richland), AMD A10-6700 (Richland)
-OS: Arch Linux 4.19 (SATA, USB), Linux Mint 19.3, Artix Linux 2019
-SeaBIOS: 1.12 and 1.13
Known problems:
- IRQ routing is done incorrect way - common problem of fam15h boards
- Windows 7 can't boot because of the incomplete ACPI implementation
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
Signed-off-by: Balazs Vinarz <vinibali1@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30987
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asus/a88xm-e/dsdt.asl')
-rw-r--r-- | src/mainboard/asus/a88xm-e/dsdt.asl | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/src/mainboard/asus/a88xm-e/dsdt.asl b/src/mainboard/asus/a88xm-e/dsdt.asl new file mode 100644 index 0000000000..aac9c84cd5 --- /dev/null +++ b/src/mainboard/asus/a88xm-e/dsdt.asl @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* DefinitionBlock Statement */ +#include <acpi/acpi.h> +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> + + /* Describe the processor tree (\_PR) */ + #include <cpu/amd/agesa/family15tn/acpi/cpu.asl> + + /* Describe the supported Sleep States for this Southbridge */ + #include <southbridge/amd/common/acpi/sleepstates.asl> + + /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */ + #include "acpi/sleep.asl" + + Scope(\_SB) { + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ + #include "acpi/routing.asl" + + Device(PCI0) { + /* Describe the AMD Northbridge */ + #include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/fch.asl> + } + + /* Describe PCI INT[A-H] for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> + + } /* End Scope(_SB) */ + + /* Describe SMBUS for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" + + /* Define the Thermal zones and methods for the platform */ + #include "acpi/thermal.asl" + + /* Define the System Indicators for the platform */ + #include "acpi/si.asl" + +} +/* End of ASL file */ |