mb/asus: Add Asus A88XM-E FM2+ with documentation

The port is based on the F2A85-M, the main differences are:
- 2 DDR3 dimms
- 2 PS/2 ports
- 2*USB2.0 and 2*USB3.0 ports
- 3+2 phase VRM
- 6 channel audio
- 6 SATA ports
- ASP1206 VRM controller
- Bolton D4 chipset
- no optical SPDIF/IO

Successfully booted configurations:
-RAM: 2*8GB Kingston KVR 1333Mhz LP, 2*8GB Crucial BLT8G3D1869DT1TX0
-CPU: AMD A8-6500 (Richland), AMD A10-6700 (Richland)
-OS:  Arch Linux 4.19 (SATA, USB), Linux Mint 19.3, Artix Linux 2019
-SeaBIOS: 1.12 and 1.13

Known problems:
- IRQ routing is done incorrect way - common problem of fam15h boards
- Windows 7 can't boot because of the incomplete ACPI implementation

Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
Signed-off-by: Balazs Vinarz <vinibali1@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30987
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

10 files changed, 455 insertions, 0 deletions

diff --git a/src/mainboard/asus/a88xm-e/acpi/cpstate.asl b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl
new file mode 100644
index 0000000000..35583de49f
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file defines the processor and performance state capability
+ * for each core in the system.  It is included into the DSDT for each
+ * core.  It assumes that each core of the system has the same performance
+ * characteristics.
+ */
+
+/*
+ * P-state support: the maximum number of P-states supported
+ * by the CPUs that we'll use - is 6. Taken from AMI BIOS.
+ */
+Name(_PSS, Package(){
+	Package()
+	{
+		0x00000D48,
+		0x00011170,
+		0x00000004,
+		0x00000004,
+		0x00000000,
+		0x00000000
+	},
+
+	Package()
+	{
+		0x00000AF0,
+		0x0000C544,
+		0x00000004,
+		0x00000004,
+		0x00000001,
+		0x00000001
+	},
+
+	Package()
+	{
+		0x000009C4,
+		0x0000B3B0,
+		0x00000004,
+		0x00000004,
+		0x00000002,
+		0x00000002
+	},
+
+	Package()
+	{
+		0x00000898,
+		0x0000ABE0,
+		0x00000004,
+		0x00000004,
+		0x00000003,
+		0x00000003
+	},
+
+	Package()
+	{
+		0x00000708,
+		0x0000A410,
+		0x00000004,
+		0x00000004,
+		0x00000004,
+		0x00000004
+	},
+
+	Package()
+	{
+		0x00000578,
+		0x00006F54,
+		0x00000004,
+		0x00000004,
+		0x00000005,
+		0x00000005
+	}
+})
+
+Name(_PCT, Package(){
+	ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+	ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+})
+
+Method(_PPC, 0){
+	Return(0)
+}
diff --git a/src/mainboard/asus/a88xm-e/acpi/gpe.asl b/src/mainboard/asus/a88xm-e/acpi/gpe.asl
new file mode 100644
index 0000000000..9f01c7a0ca
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/gpe.asl
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Scope(\_GPE) { /* Start Scope GPE */
+
+	/* General event 3 */
+	Method(_L03) {
+	}
+
+	/* Legacy PM event */
+	Method(_L08) {
+	}
+
+	/* Temp warning (TWarn) event */
+	Method(_L09) {
+	}
+
+	/* USB controller PME# */
+	Method(_L0B) {
+		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+
+	/* ExtEvent0 SCI event */
+	Method(_L10) {
+	}
+
+	/* ExtEvent1 SCI event */
+	Method(_L11) {
+	}
+
+	/* GPIO0 or GEvent8 event */
+	Method(_L18) {
+		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+
+	/* Azalia SCI event */
+	Method(_L1B) {
+		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+} /* End Scope GPE */
diff --git a/src/mainboard/asus/a88xm-e/acpi/mainboard.asl b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl
new file mode 100644
index 0000000000..699bc6b031
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+	/* Data to be patched by the BIOS during POST */
+	/* FIXME the patching is not done yet! */
+	/* Memory related values */
+	Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
+	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+	Name(PBLN, 0x0)	/* Length of BIOS area */
+
+	/* Base address of PCIe config space */
+	Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)
+	/* Length of PCIe config space, 1MB each bus */
+	Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER))
+	/* Base address of HPET table */
+	Name(HPBA, 0xFED00000)
+
+	/* Some global data */
+	Name(OSVR, 3)   /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+	Name(OSV, Ones) /* Assume nothing */
+	Name(PMOD, One) /* Assume APIC */
diff --git a/src/mainboard/asus/a88xm-e/acpi/routing.asl b/src/mainboard/asus/a88xm-e/acpi/routing.asl
new file mode 100644
index 0000000000..99511c5a21
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/routing.asl
@@ -0,0 +1,246 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+	/* Routing is in System Bus scope */
+	Name(PR0, Package(){
+		/* NB devices */
+		/* Bus 0, Dev 0 - F15 Host Controller */
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+		Package(){0x0001FFFF, 0, INTB, 0 },
+		Package(){0x0001FFFF, 1, INTC, 0 },
+
+		/* Bus 0, Dev 2 - PCIe Bridge for x16 slot */
+		Package(){0x0002FFFF, 0, INTC, 0 },
+		Package(){0x0002FFFF, 1, INTD, 0 },
+		Package(){0x0002FFFF, 2, INTA, 0 },
+		Package(){0x0002FFFF, 3, INTB, 0 },
+
+		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
+		/* Bus 0, Dev 4 - PCIe Bridge for 4x slot */
+		Package(){0x0004FFFF, 0, INTA, 0 },
+		Package(){0x0004FFFF, 1, INTB, 0 },
+		Package(){0x0004FFFF, 2, INTC, 0 },
+		Package(){0x0004FFFF, 3, INTD, 0 },
+
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+		/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+		/* Bus 0, Dev 20 -
+		 *        F0: SMBus/ACPI, F1: IDE, F2: HDAudio, F3: LPC, F4: PCIBridge, F5: USB
+		 */
+		Package(){0x0014FFFF, 0, INTA, 0 },
+		Package(){0x0014FFFF, 1, INTB, 0 },
+		Package(){0x0014FFFF, 2, INTC, 0 },
+		Package(){0x0014FFFF, 3, INTD, 0 },
+
+		/* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0, EHCI @ func 2 */
+		Package(){0x0012FFFF, 0, INTC, 0 },
+		Package(){0x0012FFFF, 1, INTB, 0 },
+
+		Package(){0x0013FFFF, 0, INTC, 0 },
+		Package(){0x0013FFFF, 1, INTB, 0 },
+
+		Package(){0x0016FFFF, 0, INTC, 0 },
+		Package(){0x0016FFFF, 1, INTB, 0 },
+
+		/* SB devices */
+		/* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
+		Package(){0x0010FFFF, 0, INTC, 0 },
+		Package(){0x0010FFFF, 1, INTB, 0 },
+
+		/* Bus 0, Dev 17 - SATA controller */
+		Package(){0x0011FFFF, 0, INTD, 0 },
+
+		/* Bus 0, Dev 21 PCIe Bridge */
+		Package(){0x0015FFFF, 0, INTA, 0 },
+		Package(){0x0015FFFF, 1, INTB, 0 },
+		Package(){0x0015FFFF, 2, INTC, 0 },
+		Package(){0x0015FFFF, 3, INTD, 0 },
+	})
+
+	Name(APR0, Package(){
+		/* NB devices in APIC mode */
+		/* Bus 0, Dev 0 - F15 Host Controller */
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
+
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+		Package(){0x0001FFFF, 0, 0, 17 },
+		Package(){0x0001FFFF, 1, 0, 18 },
+
+		/* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */
+		Package(){0x0002FFFF, 0, 0, 18 },
+		Package(){0x0002FFFF, 1, 0, 19 },
+		Package(){0x0002FFFF, 2, 0, 16 },
+		Package(){0x0002FFFF, 3, 0, 17 },
+
+		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
+		/* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */
+		Package(){0x0004FFFF, 0, 0, 16 },
+		Package(){0x0004FFFF, 1, 0, 17 },
+		Package(){0x0004FFFF, 2, 0, 18 },
+		Package(){0x0004FFFF, 3, 0, 19 },
+
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+		/* Bus 0, Dev 7 - PCIe Bridge for network card */
+		/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+		/* Bus 0, Dev 20 -
+		 *        F0: SMBus/ACPI, F1: IDE, F2: HDAudio, F3: LPC, F4: PCIBridge, F5: USB
+		 */
+		Package(){0x0014FFFF, 0, 0, 16 },
+		Package(){0x0014FFFF, 1, 0, 17 },
+		Package(){0x0014FFFF, 2, 0, 18 },
+		Package(){0x0014FFFF, 3, 0, 19 },
+
+		/* SB devices in APIC mode */
+		/* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0, EHCI @ func 2 */
+		Package(){0x0012FFFF, 0, 0, 18 },
+		Package(){0x0012FFFF, 1, 0, 17 },
+
+		Package(){0x0013FFFF, 0, 0, 18 },
+		Package(){0x0013FFFF, 1, 0, 17 },
+
+		Package(){0x0016FFFF, 0, 0, 18 },
+		Package(){0x0016FFFF, 1, 0, 17 },
+
+		/* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
+		Package(){0x0010FFFF, 0, 0, 0x12},
+		Package(){0x0010FFFF, 1, 0, 0x11},
+
+		/* Bus 0, Dev 17 - SATA controller */
+		Package(){0x0011FFFF, 0, 0, 19 },
+
+		/* Bus 0, Dev 21 PCIE Bridge */
+		Package(){0x0015FFFF, 0, 0, 17 },
+		Package(){0x0015FFFF, 1, 0, 18 },
+		Package(){0x0015FFFF, 2, 0, 19 },
+		Package(){0x0015FFFF, 3, 0, 16 },
+	})
+
+	Name(PS2, Package(){
+		/* The external GFX - Hooked to PCIe slot 2 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+	Name(APS2, Package(){
+		/* The external GFX - Hooked to PCIe slot 2 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	/* black slot */
+	Name(PS4, Package(){
+		/* PCIe slot - Hooked to PCIe slot 4 */
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+	})
+	Name(APS4, Package(){
+		/* PCIe slot - Hooked to PCIe slot 4 */
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
+	})
+
+	Name(PS5, Package(){
+		/* PCIe slot - Hooked to PCIe slot 5 */
+		Package(){0x0000FFFF, 0, INTB, 0 },
+		Package(){0x0000FFFF, 1, INTC, 0 },
+		Package(){0x0000FFFF, 2, INTD, 0 },
+		Package(){0x0000FFFF, 3, INTA, 0 },
+	})
+	Name(APS5, Package(){
+		/* PCIe slot - Hooked to PCIe slot 5 */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PS6, Package(){
+		/* PCIe slot - Hooked to PCIe slot 6 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+	Name(APS6, Package(){
+		/* PCIe slot - Hooked to PCIe slot 6 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS7, Package(){
+		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+
+	Name(APS7, Package(){
+		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, 0, 19 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
+	})
+
+	Name(PBR0, Package(){
+		/* PCIx1 on SB */
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+	})
+	Name(ABR0, Package(){
+		/* PCIx1 on SB */
+		Package(){0x0000FFFF, 0, 0, 0x10 },
+		Package(){0x0000FFFF, 1, 0, 0x11 },
+		Package(){0x0000FFFF, 2, 0, 0x12 },
+		Package(){0x0000FFFF, 3, 0, 0x13 },
+	})
+
+	Name(PBR1, Package(){
+		/* Onboard network */
+		Package(){0x0000FFFF, 0, INTB, 0 },
+		Package(){0x0000FFFF, 1, INTC, 0 },
+		Package(){0x0000FFFF, 2, INTD, 0 },
+		Package(){0x0000FFFF, 3, INTA, 0 },
+	})
+	Name(ABR1, Package(){
+		/* Onboard network */
+		Package(){0x0000FFFF, 0, 0, 0x11 },
+		Package(){0x0000FFFF, 1, 0, 0x12 },
+		Package(){0x0000FFFF, 2, 0, 0x13 },
+		Package(){0x0000FFFF, 3, 0, 0x10 },
+	})
+
+	/* SB PCI Bridge  */
+	Name(PCIB, Package(){
+		/* PCI slots: slot 0 behind Dev14, Fun4. */
+		Package(){0x0005FFFF, 0, 0, 0x14 },
+		Package(){0x0005FFFF, 1, 0, 0x15 },
+		Package(){0x0005FFFF, 2, 0, 0x16 },
+		Package(){0x0005FFFF, 3, 0, 0x17 },
+	})
diff --git a/src/mainboard/asus/a88xm-e/acpi/sata.asl b/src/mainboard/asus/a88xm-e/acpi/sata.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/sata.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/si.asl b/src/mainboard/asus/a88xm-e/acpi/si.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/si.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/sleep.asl b/src/mainboard/asus/a88xm-e/acpi/sleep.asl
new file mode 100644
index 0000000000..87773378c9
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/sleep.asl
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+ * \_PTS - Prepare to Sleep method
+ *
+ *	Entry:
+ *		Arg0=The value of the sleeping state S1=1, S2=2, etc
+ *
+ * Exit:
+ *		-none-
+ *
+ * The _PTS control method is executed at the beginning of the sleep process
+ * for S1-S5. The sleeping value is passed to the _PTS control method.  This
+ * control method may be executed a relatively long time before entering the
+ * sleep state and the OS may abort the operation without notification to
+ * the ACPI driver.  This method cannot modify the configuration or power
+ * state of any device in the system.
+ */
+Method(\_PTS, 1) {
+
+	/* Clear wake status structure. */
+	Store(0, Index(WKST,0))
+	Store(0, Index(WKST,1))
+
+	Store (0x07, UPWS)
+} /* End Method(\_PTS) */
+
+/*
+ *  \_WAK System Wake method
+ *
+ *	Entry:
+ *		Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ *	Exit:
+ *		Return package of 2 DWords
+ *		Dword 1 - Status
+ *			0x00000000	wake succeeded
+ *			0x00000001	Wake was signaled but failed due to lack of power
+ *			0x00000002	Wake was signaled but failed due to thermal condition
+ *		Dword 2 - Power Supply state
+ *			if non-zero the effective S-state the power supply entered
+ */
+Method(\_WAK, 1) {
+	Return(WKST)
+} /* End Method(\_WAK) */
diff --git a/src/mainboard/asus/a88xm-e/acpi/superio.asl b/src/mainboard/asus/a88xm-e/acpi/superio.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/superio.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/thermal.asl b/src/mainboard/asus/a88xm-e/acpi/thermal.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/thermal.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
new file mode 100644
index 0000000000..d90fffdd40
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* USB overcurrent mapping pins. */
+Name(UOM0, 0)
+Name(UOM1, 2)
+Name(UOM2, 0)
+Name(UOM3, 7)
+Name(UOM4, 2)
+Name(UOM5, 2)
+Name(UOM6, 6)
+Name(UOM7, 2)
+Name(UOM8, 6)
+Name(UOM9, 6)