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authorBalazs Vinarz <vinibali1@gmail.com>2019-01-18 10:53:13 +0100
committerAngel Pons <th3fanbus@gmail.com>2020-08-13 17:34:04 +0000
commitffa710b9dd241cc7545858a2ac69f7cdb214cddf (patch)
tree270c3262c06d9bf4280f46081d343a8e14e548b4 /src/mainboard/asus/a88xm-e/acpi/mainboard.asl
parent414d7e4642991696dc81fbcb7ac68fe75fa4bc12 (diff)
mb/asus: Add Asus A88XM-E FM2+ with documentation
The port is based on the F2A85-M, the main differences are: - 2 DDR3 dimms - 2 PS/2 ports - 2*USB2.0 and 2*USB3.0 ports - 3+2 phase VRM - 6 channel audio - 6 SATA ports - ASP1206 VRM controller - Bolton D4 chipset - no optical SPDIF/IO Successfully booted configurations: -RAM: 2*8GB Kingston KVR 1333Mhz LP, 2*8GB Crucial BLT8G3D1869DT1TX0 -CPU: AMD A8-6500 (Richland), AMD A10-6700 (Richland) -OS: Arch Linux 4.19 (SATA, USB), Linux Mint 19.3, Artix Linux 2019 -SeaBIOS: 1.12 and 1.13 Known problems: - IRQ routing is done incorrect way - common problem of fam15h boards - Windows 7 can't boot because of the incomplete ACPI implementation Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90 Signed-off-by: Balazs Vinarz <vinibali1@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30987 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asus/a88xm-e/acpi/mainboard.asl')
-rw-r--r--src/mainboard/asus/a88xm-e/acpi/mainboard.asl20
1 files changed, 20 insertions, 0 deletions
diff --git a/src/mainboard/asus/a88xm-e/acpi/mainboard.asl b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl
new file mode 100644
index 0000000000..699bc6b031
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+ /* Data to be patched by the BIOS during POST */
+ /* FIXME the patching is not done yet! */
+ /* Memory related values */
+ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+ Name(PBLN, 0x0) /* Length of BIOS area */
+
+ /* Base address of PCIe config space */
+ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)
+ /* Length of PCIe config space, 1MB each bus */
+ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER))
+ /* Base address of HPET table */
+ Name(HPBA, 0xFED00000)
+
+ /* Some global data */
+ Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+ Name(OSV, Ones) /* Assume nothing */
+ Name(PMOD, One) /* Assume APIC */