Remove all AMD K8 boards

Platforms with LATE_CBMEM_INIT were agreed to be
removed with 4.7 release late 2017.

Change-Id: I0ecbb40f8c7ebdf68217f50af5624905d9005c64
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

17 files changed, 0 insertions, 2085 deletions

diff --git a/src/mainboard/asrock/939a785gmh/Kconfig b/src/mainboard/asrock/939a785gmh/Kconfig
deleted file mode 100644
index 2148385def..0000000000
--- a/src/mainboard/asrock/939a785gmh/Kconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-if BOARD_ASROCK_939A785GMH
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_AMD_SOCKET_939
-	select K8_HT_FREQ_1G_SUPPORT
-	select NORTHBRIDGE_AMD_AMDK8
-	select SOUTHBRIDGE_AMD_RS780
-	select SOUTHBRIDGE_AMD_SB700
-	select SUPERIO_WINBOND_W83627DHG
-	select HAVE_ACPI_TABLES
-	select HAVE_ACPI_RESUME
-	select HAVE_MP_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_OPTION_TABLE
-	select LIFT_BSP_APIC_ID
-	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
-	select BOARD_ROMSIZE_KB_1024
-	select GFXUMA
-	select RAMINIT_SYSINFO
-	select QRANK_DIMM_SUPPORT
-	select SET_FIDVID
-
-config MAINBOARD_DIR
-	string
-	default asrock/939a785gmh
-
-config DCACHE_RAM_BASE
-	hex
-	default 0xc8000
-
-config DCACHE_RAM_SIZE
-	hex
-	default 0x08000
-
-config APIC_ID_OFFSET
-	hex
-	default 0x0
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "939A785GMH"
-
-config MAX_CPUS
-	int
-	default 8
-
-config MAX_PHYSICAL_CPUS
-	int
-	default 2
-
-config HT_CHAIN_END_UNITID_BASE
-	hex
-	default 0x1
-
-config HT_CHAIN_UNITID_BASE
-	hex
-	default 0x0
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-endif # BOARD_ASROCK_939A785GMH
diff --git a/src/mainboard/asrock/939a785gmh/Kconfig.name b/src/mainboard/asrock/939a785gmh/Kconfig.name
deleted file mode 100644
index 270239120f..0000000000
--- a/src/mainboard/asrock/939a785gmh/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASROCK_939A785GMH
-	bool "939A785GMH/128M"
diff --git a/src/mainboard/asrock/939a785gmh/acpi/ide.asl b/src/mainboard/asrock/939a785gmh/acpi/ide.asl
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/asrock/939a785gmh/acpi/ide.asl
+++ /dev/null
diff --git a/src/mainboard/asrock/939a785gmh/acpi/routing.asl b/src/mainboard/asrock/939a785gmh/acpi/routing.asl
deleted file mode 100644
index 65afe39b7a..0000000000
--- a/src/mainboard/asrock/939a785gmh/acpi/routing.asl
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
-		)
-	{
-		#include "routing.asl"
-	}
-*/
-
-/* Routing is in System Bus scope */
-Scope(\_SB) {
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-
-		Package(){0x0002FFFF, 0, INTC, 0 },
-		Package(){0x0002FFFF, 1, INTD, 0 },
-		Package(){0x0002FFFF, 2, INTA, 0 },
-		Package(){0x0002FFFF, 3, INTB, 0 },
-
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, INTA, 0 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, INTA, 0 },
-		Package(){0x0012FFFF, 1, INTB, 0 },
-		Package(){0x0012FFFF, 2, INTC, 0 },
-		Package(){0x0012FFFF, 3, INTD, 0 },
-
-		Package(){0x0013FFFF, 0, INTC, 0 },
-		Package(){0x0013FFFF, 1, INTD, 0 },
-		Package(){0x0013FFFF, 2, INTA, 0 },
-		Package(){0x0013FFFF, 3, INTB, 0 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - RS780 Host Controller */
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
-		/* Package(){0x0001FFFF, 0, 0, 18 }, */
-		/* Package(){0x0001FFFF, 1, 0, 19 }, */
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, 0, 18 },
-		Package(){0x0002FFFF, 1, 0, 19 },
-		Package(){0x0002FFFF, 2, 0, 16 },
-		Package(){0x0002FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 9 - PCIe x1 slot  */
-		Package(){0x0009FFFF, 0, 0, 17 },
-		Package(){0x0009FFFF, 1, 0, 18 },
-		Package(){0x0009FFFF, 2, 0, 19 },
-		Package(){0x0009FFFF, 3, 0, 10 },
-
-		/* Bus 0, Dev A - PCIe internal ethernet */
-		Package(){0x000AFFFF, 0, 0, 18 },
-		Package(){0x000AFFFF, 1, 0, 19 },
-		Package(){0x000AFFFF, 2, 0, 16 },
-		Package(){0x000AFFFF, 3, 0, 17 },
-		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 17 - SATA controller #2 */
-		/* Bus 0, Dev 18 - SATA controller #1 */
-		Package(){0x0011FFFF, 0, 0, 22 },
-
-		/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
-		 * EHCI, dev 18, 19 func 2 */
-		Package(){0x0012FFFF, 0, 0, 16 },
-		Package(){0x0012FFFF, 1, 0, 17 },
-		Package(){0x0012FFFF, 2, 0, 18 },
-		Package(){0x0012FFFF, 3, 0, 19 },
-
-		Package(){0x0013FFFF, 0, 0, 18 },
-		Package(){0x0013FFFF, 1, 0, 19 },
-		Package(){0x0013FFFF, 2, 0, 16 },
-		Package(){0x0013FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, 0, 16 },
-		Package(){0x0014FFFF, 1, 0, 17 },
-		Package(){0x0014FFFF, 2, 0, 18 },
-		Package(){0x0014FFFF, 3, 0, 19 },
-	})
-
-	Name(PR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, INTC, 0 },
-		Package(){0x0005FFFF, 1, INTD, 0 },
-		Package(){0x0005FFFF, 2, INTA, 0 },
-		Package(){0x0005FFFF, 3, INTB, 0 },
-	})
-
-	Name(APR1, Package(){
-		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
-		Package(){0x0005FFFF, 0, 0, 18 },
-		Package(){0x0005FFFF, 1, 0, 19 },
-		Package(){0x0005FFFF, 2, 0, 16 },
-		Package(){0x0005FFFF, 3, 0, 11 },
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS9, Package(){
-		/* PCIe slot - Hooked to PCIe x1 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-
-	Name(APS9, Package(){
-		/* PCIe slot - Hooked to PCIe x1 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-	Name(PSa, Package(){
-		/* PCIe slot - Hooked to ethernet */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-
-	Name(APSa, Package(){
-		/* PCIe slot - Hooked to PCIe slot 10 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PCIB, Package(){
-		/* PCI slots: slot 0, slot 1, behind Dev14, Fun4. */
-		Package(){0x0005FFFF, 0, 0, 0x14 },
-		Package(){0x0005FFFF, 1, 0, 0x15 },
-		Package(){0x0005FFFF, 2, 0, 0x16 },
-		Package(){0x0005FFFF, 3, 0, 0x17 },
-		Package(){0x0006FFFF, 0, 0, 0x15 },
-		Package(){0x0006FFFF, 1, 0, 0x16 },
-		Package(){0x0006FFFF, 2, 0, 0x17 },
-		Package(){0x0006FFFF, 3, 0, 0x14 },
-	})
-}
diff --git a/src/mainboard/asrock/939a785gmh/acpi/sata.asl b/src/mainboard/asrock/939a785gmh/acpi/sata.asl
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/asrock/939a785gmh/acpi/sata.asl
+++ /dev/null
diff --git a/src/mainboard/asrock/939a785gmh/acpi/usb.asl b/src/mainboard/asrock/939a785gmh/acpi/usb.asl
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/asrock/939a785gmh/acpi/usb.asl
+++ /dev/null
diff --git a/src/mainboard/asrock/939a785gmh/acpi_tables.c b/src/mainboard/asrock/939a785gmh/acpi_tables.c
deleted file mode 100644
index 6026a68ef9..0000000000
--- a/src/mainboard/asrock/939a785gmh/acpi_tables.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include "northbridge/amd/amdk8/acpi.h"
-#include <arch/cpu.h>
-#include <cpu/amd/powernow.h>
-#include <southbridge/amd/sb700/sb700.h>
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	get_bus_conf();
-
-	/* create all subtables for processors */
-	current = acpi_create_madt_lapics(current);
-
-	/* Write SB700 IOAPIC, only one */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
-					   IO_APIC_ADDR, 0);
-
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 0, 2, 0);
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 9, 9, 0xF);
-	/* 0: mean bus 0--->ISA */
-	/* 0: PIC 0 */
-	/* 2: APIC 2 */
-	/* 5 mean: 0101 --> Edge-triggered, Active high */
-
-	/* create all subtables for processors */
-	/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
-	/* 1: LINT1 connect to NMI */
-
-	return current;
-}
diff --git a/src/mainboard/asrock/939a785gmh/board_info.txt b/src/mainboard/asrock/939a785gmh/board_info.txt
deleted file mode 100644
index 0335c9bec1..0000000000
--- a/src/mainboard/asrock/939a785gmh/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Board name: 939A785GMH/128M
-Category: desktop
-Board URL: http://www.asrock.com/mb/overview.asp?Model=939A785GMH/128M&s=939
-ROM package: DIP8
-ROM protocol: SPI
-Release year: 2009
diff --git a/src/mainboard/asrock/939a785gmh/cmos.layout b/src/mainboard/asrock/939a785gmh/cmos.layout
deleted file mode 100644
index e22e68a15a..0000000000
--- a/src/mainboard/asrock/939a785gmh/cmos.layout
+++ /dev/null
@@ -1,69 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2010 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-##
-##
-
-entries
-
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#392          3       r       0        unused
-395          1       e       1        hw_scrubber
-396          1       e       1        interleave_chip_selects
-397          2       e       8        max_mem_clock
-399          1       e       2        multi_core
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-440          4       e       9        slow_cpu
-444          1       e       1        nmi
-445          1       e       1        iommu
-456          1       e       1        ECC_memory
-728        256       h       0        user_data
-984         16       h       0        check_sum
-# Reserve the extended AMD configuration registers
-1000        24       r       0        amd_reserved
-
-
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     5     Notice
-6     6     Info
-6     7     Debug
-6     8     Spew
-8     0     DDR400
-8     1     DDR333
-8     2     DDR266
-8     3     DDR200
-9     0     off
-9     1     87.5%
-9     2     75.0%
-9     3     62.5%
-9     4     50.0%
-9     5     37.5%
-9     6     25.0%
-9     7     12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asrock/939a785gmh/devicetree.cb b/src/mainboard/asrock/939a785gmh/devicetree.cb
deleted file mode 100644
index 8b40b9f6d4..0000000000
--- a/src/mainboard/asrock/939a785gmh/devicetree.cb
+++ /dev/null
@@ -1,131 +0,0 @@
-#Define gppsb_configuration,	A=0, B=1, C=2, D=3, E=4(default)
-#Define gpp_configuration -> device 9 1x and device a 1x is 3 and device 9 2x is 2
-#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
-#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
-#			1: the system allows a PCIE link to be established on Dev2 or Dev3.
-#Define gfx_dual_slot, 0: single slot, 1: dual slot (means if GFX slot are two 2 8x slots)
-#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
-#Define gfx_tmds, 0: didn't support TMDS, 1: support
-#Define gfx_compliance, 0: didn't support compliance, 1: support
-#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
-#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
-chip northbridge/amd/amdk8/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/socket_939
-		device lapic 0 on end
-		end
-	end
-	device domain 0 on
-		subsystemid 0x1022 0x3060 inherit
-		chip northbridge/amd/amdk8
-			device pci 18.0 on #  southbridge
-				chip southbridge/amd/rs780
-					device pci 0.0 on end # HT  	0x9600
-					device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
-					device pci 2.0 on end # PCIE P2P bridge 16x slot
-					device pci 3.0 off end # used in dual slot config
-					device pci 4.0 off end # GPPSB
-					device pci 5.0 off end # GPPSB
-					device pci 6.0 off end # GPPSB
-					device pci 7.0 off end # GPPSB
-					device pci 8.0 off end # NB/SB Link P2P bridge
-					device pci 9.0 on end # GPP for x1 slot
-					device pci a.0 on end # GPP for internal network adapter
-					register "gppsb_configuration" = "4"   # Configuration ?
-					register "gpp_configuration" = "3"   # Configuration D default
-					register "port_enable" = "0x60c"
-					register "gfx_dev2_dev3" = "1"
-					register "gfx_dual_slot" = "0"
-					register "gfx_lane_reversal" = "0"
-					register "gfx_tmds" = "0"
-					register "gfx_compliance" = "0"
-					register "gfx_reconfiguration" = "1"
-					register "gfx_link_width" = "0"
-				end
-				chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus
-					device pci 11.0 on end # SATA
-					device pci 12.0 on end # USB
-					device pci 12.1 on end # USB
-					device pci 12.2 on end # USB
-					device pci 13.0 on end # USB
-					device pci 13.1 on end # USB
-					device pci 13.2 on end # USB
-	 				device pci 14.0 on # SM
-						chip drivers/generic/generic #dimm 0-0-0
-							device i2c 50 on end
-						end
-						chip drivers/generic/generic #dimm 0-0-1
-							device i2c 51 on end
-						end
-						chip drivers/generic/generic #dimm 0-1-0
-							device i2c 52 on end
-						end
-						chip drivers/generic/generic #dimm 0-1-1
-							device i2c 53 on end
-						end
-					end # SM
-					device pci 14.1 on end # IDE    0x439c
-					device pci 14.2 on end # HDA    0x4383
-					device pci 14.3 on # LPC	0x439d
-
-						chip superio/winbond/w83627dhg
-							device pnp 2e.0 off #  Floppy
-								io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 2e.1 off #  Parallel Port
-								io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 2e.2 on #  Com1
-								io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.3 on #  Com2
-								io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							device pnp 2e.5 on #  PS/2 keyboard & mouse
-								io 0x60 = 0x60
-								io 0x62 = 0x64
-								irq 0x70 = 1
-							end
-							#device pnp 2e.6 off #  SPI
-							#end
-							device pnp 2e.307 off #  GPIO6
-							end
-							device pnp 2e.8 on #  WDTO#, PLED
-							end
-							device pnp 2e.009 on #  GPIO2
-							end
-							device pnp 2e.109 on #  GPIO3
-							end
-							device pnp 2e.209 on #  GPIO4
-							end
-							device pnp 2e.309 off #  GPIO5
-							end
-							device pnp 2e.a off #  ACPI
-							end
-							device pnp 2e.b on # HWM
-								io 0x60 = 0x290
-							end
-							device pnp 2e.c off # PECI, SST
-							end
-						end	#superio/winbond/w8362
-
-					end		#LPC
-					device pci 14.4 on end # PCI 0x4384
-					device pci 14.5 on end # USB 2
-					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
-				end	#southbridge/amd/sb700
-			end #  device pci 18.0
-
-			device pci 18.0 on end
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end		#northbridge/amd/amdk8
-	end #domain
-end		#northbridge/amd/amdk8/root_complex
diff --git a/src/mainboard/asrock/939a785gmh/dsdt.asl b/src/mainboard/asrock/939a785gmh/dsdt.asl
deleted file mode 100644
index 9c50f96386..0000000000
--- a/src/mainboard/asrock/939a785gmh/dsdt.asl
+++ /dev/null
@@ -1,634 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* DefinitionBlock Statement */
-DefinitionBlock (
-	"DSDT.AML",	/* Output filename */
-	"DSDT",		/* Signature */
-	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
-	"ASROCK",	/* OEMID */
-	"COREBOOT",	/* TABLE ID */
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	/* #include <arch/x86/acpi/debug.asl> */		/* Include global debug methods if needed */
-	#include "northbridge/amd/amdk8/util.asl"
-
-	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
-
-	Name(PMOD, One)	/* Assume APIC */
-
-	/* PIC IRQ mapping registers, C00h-C01h */
-	OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
-		Field(PRQM, ByteAcc, NoLock, Preserve) {
-		PRQI, 0x00000008,
-		PRQD, 0x00000008,  /* Offset: 1h */
-	}
-	IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
-		PINA, 0x00000008,	/* Index 0 */
-		PINB, 0x00000008,	/* Index 1 */
-		PINC, 0x00000008,	/* Index 2 */
-		PIND, 0x00000008,	/* Index 3 */
-		AINT, 0x00000008,	/* Index 4 */
-		SINT, 0x00000008,	/* Index 5 */
-		, 0x00000008,		/* Index 6 */
-		AAUD, 0x00000008,	/* Index 7 */
-		AMOD, 0x00000008,	/* Index 8 */
-		PINE, 0x00000008,	/* Index 9 */
-		PINF, 0x00000008,	/* Index A */
-		PING, 0x00000008,	/* Index B */
-		PINH, 0x00000008,	/* Index C */
-	}
-
-	#include "acpi/routing.asl"
-
-	Scope(\_SB) {
-
-		Method(_PIC, 0x01, NotSerialized)
-		{
-			If (Arg0)
-			{
-				\_SB.CIRQ()
-			}
-			Store(Arg0, PMOD)
-		}
-
-		Method(CIRQ, 0x00, NotSerialized){
-			Store(0, PINA)
-			Store(0, PINB)
-			Store(0, PINC)
-			Store(0, PIND)
-			Store(0, PINE)
-			Store(0, PINF)
-			Store(0, PING)
-			Store(0, PINH)
-		}
-
-		Name(IRQB, ResourceTemplate(){
-			IRQ(Level,ActiveLow,Shared){15}
-		})
-
-		Name(IRQP, ResourceTemplate(){
-			IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
-		})
-
-		Name(PITF, ResourceTemplate(){
-			IRQ(Level,ActiveLow,Exclusive){9}
-		})
-
-		Device(INTA) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 1)
-
-			Method(_STA, 0) {
-				if (PINA) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTA._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKA\\_DIS\n") */
-				Store(0, PINA)
-			} /* End Method(_SB.INTA._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKA\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTA._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINA, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTA._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINA)
-			} /* End Method(_SB.INTA._SRS) */
-		} /* End Device(INTA) */
-
-		Device(INTB) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 2)
-
-			Method(_STA, 0) {
-				if (PINB) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTB._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKB\\_DIS\n") */
-				Store(0, PINB)
-			} /* End Method(_SB.INTB._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKB\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTB._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINB, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTB._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINB)
-			} /* End Method(_SB.INTB._SRS) */
-		} /* End Device(INTB)  */
-
-		Device(INTC) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 3)
-
-			Method(_STA, 0) {
-				if (PINC) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTC._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKC\\_DIS\n") */
-				Store(0, PINC)
-			} /* End Method(_SB.INTC._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKC\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTC._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINC, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTC._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINC)
-			} /* End Method(_SB.INTC._SRS) */
-		} /* End Device(INTC)  */
-
-		Device(INTD) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 4)
-
-			Method(_STA, 0) {
-				if (PIND) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTD._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKD\\_DIS\n") */
-				Store(0, PIND)
-			} /* End Method(_SB.INTD._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKD\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTD._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PIND, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTD._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PIND)
-			} /* End Method(_SB.INTD._SRS) */
-		} /* End Device(INTD)  */
-
-		Device(INTE) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 5)
-
-			Method(_STA, 0) {
-				if (PINE) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTE._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKE\\_DIS\n") */
-				Store(0, PINE)
-			} /* End Method(_SB.INTE._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKE\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTE._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINE, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTE._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINE)
-			} /* End Method(_SB.INTE._SRS) */
-		} /* End Device(INTE)  */
-
-		Device(INTF) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 6)
-
-			Method(_STA, 0) {
-				if (PINF) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTF._STA) */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKF\\_DIS\n") */
-				Store(0, PINF)
-			} /* End Method(_SB.INTF._DIS) */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKF\\_PRS\n") */
-				Return(PITF)
-			} /* Method(_SB.INTF._PRS) */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINF, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTF._CRS) */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINF)
-			} /*  End Method(_SB.INTF._SRS) */
-		} /* End Device(INTF)  */
-
-		Device(INTG) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 7)
-
-			Method(_STA, 0) {
-				if (PING) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTG._STA)  */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKG\\_DIS\n") */
-				Store(0, PING)
-			} /* End Method(_SB.INTG._DIS)  */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKG\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTG._CRS)  */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PING, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTG._CRS)  */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PING)
-			} /* End Method(_SB.INTG._SRS)  */
-		} /* End Device(INTG)  */
-
-		Device(INTH) {
-			Name(_HID, EISAID("PNP0C0F"))
-			Name(_UID, 8)
-
-			Method(_STA, 0) {
-				if (PINH) {
-					Return(0x0B) /* sata is invisible */
-				} else {
-					Return(0x09) /* sata is disabled */
-				}
-			} /* End Method(_SB.INTH._STA)  */
-
-			Method(_DIS ,0) {
-				/* DBGO("\\_SB\\LNKH\\_DIS\n") */
-				Store(0, PINH)
-			} /* End Method(_SB.INTH._DIS)  */
-
-			Method(_PRS ,0) {
-				/* DBGO("\\_SB\\LNKH\\_PRS\n") */
-				Return(IRQP)
-			} /* Method(_SB.INTH._CRS)  */
-
-			Method(_CRS ,0) {
-				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
-				CreateWordField(IRQB, 0x1, IRQN)
-				ShiftLeft(1, PINH, IRQN)
-				Return(IRQB)
-			} /* Method(_SB.INTH._CRS)  */
-
-			Method(_SRS, 1) {
-				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
-				CreateWordField(ARG0, 1, IRQM)
-
-				/* Use lowest available IRQ */
-				FindSetRightBit(IRQM, Local0)
-				if (Local0) {
-					Decrement(Local0)
-				}
-				Store(Local0, PINH)
-			} /* End Method(_SB.INTH._SRS)  */
-		} /* End Device(INTH)   */
-
-	}   /* End Scope(_SB)  */
-
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Wake status package */
-
-	Name(WKST,Package(){Zero, Zero})
-
-	/* System Bus */
-	Scope(\_SB) { /* Start \_SB scope */
-		#include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
-
-		/*  _SB.PCI0 */
-		/* Note: Only need HID on Primary Bus */
-		Device(PCI0) {
-
-			Name(_HID, EISAID("PNP0A03"))
-			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
-			Method(_BBN, 0) { /* Bus number = 0 */
-				Return(0)
-			}
-			Method(_STA, 0) {
-				/* DBGO("\\_SB\\PCI0\\_STA\n") */
-				Return(0x0B)     /* Status is visible */
-			}
-
-			Method(_PRT,0) {
-				If(PMOD){ Return(APR0) }   /* APIC mode */
-				Return (PR0)                  /* PIC Mode */
-			} /* end _PRT */
-
-			/* Describe the Northbridge devices */
-			Device(AMRT) {
-				Name(_ADR, 0x00000000)
-			} /* end AMRT */
-
-			/* The internal GFX bridge */
-			Device(AGPB) {
-				Name(_ADR, 0x00010000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					Return (APR1)
-				}
-			}  /* end AGPB */
-
-			/* The external GFX bridge */
-			Device(PBR2) {
-				Name(_ADR, 0x00020000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APS2) }   /* APIC mode */
-					Return (PS2)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR2 */
-
-			/* GPP x1 */
-			Device(PBR9) {
-				Name(_ADR, 0x00090000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APS9) }   /* APIC mode */
-					Return (PS9)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBR9 */
-
-			/* ethernet */
-			Device(PBRa) {
-				Name(_ADR, 0x000A0000)
-				Name(_PRW, Package() {0x18, 4})
-				Method(_PRT,0) {
-					If(PMOD){ Return(APSa) }   /* APIC mode */
-					Return (PSa)                  /* PIC Mode */
-				} /* end _PRT */
-			} /* end PBRa */
-
-
-			/* PCI slot 1, 2, 3 */
-			Device(PIBR) {
-				Name(_ADR, 0x00140004)
-				Name(_PRW, Package() {0x18, 4})
-
-				Method(_PRT, 0) {
-					Return (PCIB)
-				}
-			}
-
-			Device(LIBR) {
-				Name(_ADR, 0x00140003)
-				/* Method(_INI) {
-				*	DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
-				} */ /* End Method(_SB.SBRDG._INI) */
-
-				/* Real Time Clock Device */
-				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
-					Name(_CRS, ResourceTemplate() {
-						IRQNoFlags(){8}
-						IO(Decode16,0x0070, 0x0070, 0, 2)
-						/* IO(Decode16,0x0070, 0x0070, 0, 4) */
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
-
-				Device(TMR) {	/* Timer */
-					Name(_HID,EISAID("PNP0100"))	/* System Timer */
-					Name(_CRS, ResourceTemplate() {
-						IRQNoFlags(){0}
-						IO(Decode16, 0x0040, 0x0040, 0, 4)
-						/* IO(Decode16, 0x0048, 0x0048, 0, 4) */
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
-
-				Device(SPKR) {	/* Speaker */
-					Name(_HID,EISAID("PNP0800"))	/* AT style speaker */
-					Name(_CRS, ResourceTemplate() {
-						IO(Decode16, 0x0061, 0x0061, 0, 1)
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
-
-				Device(PIC) {
-					Name(_HID,EISAID("PNP0000"))	/* AT Interrupt Controller */
-					Name(_CRS, ResourceTemplate() {
-						IRQNoFlags(){2}
-						IO(Decode16,0x0020, 0x0020, 0, 2)
-						IO(Decode16,0x00A0, 0x00A0, 0, 2)
-						/* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
-						/* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
-
-				Device(MAD) { /* 8257 DMA */
-					Name(_HID,EISAID("PNP0200"))	/* Hardware Device ID */
-					Name(_CRS, ResourceTemplate() {
-						DMA(Compatibility,BusMaster,Transfer8){4}
-						IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
-						IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
-						IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
-						IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
-						IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
-						IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
-					}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
-				} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
-
-				Device(COPR) {
-					Name(_HID,EISAID("PNP0C04"))	/* Math Coprocessor */
-					Name(_CRS, ResourceTemplate() {
-						IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
-						IRQNoFlags(){13}
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-
-				Device(HPTM) {
-					Name(_HID,EISAID("PNP0103"))
-					Name(CRS,ResourceTemplate()	{
-						Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT)	/* 1kb reserved space */
-					})
-					Method(_STA, 0) {
-						Return(0x0F) /* sata is visible */
-					}
-					Method(_CRS, 0)	{
-						CreateDwordField(CRS, ^HPT._BAS, HPBX)
-						Store(HPBA, HPBX)
-						Return(CRS)
-					}
-				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-			} /* end LIBR */
-
-		    External (BUSN)
-		    External (MMIO)
-		    External (PCIO)
-		    External (SBLK)
-		    External (TOM1)
-		    External (HCLK)
-		    External (SBDN)
-		    External (HCDN)
-
-		    Method (_CRS, 0, NotSerialized)
-			{
-			    Name (BUF0, ResourceTemplate ()
-			    {
-				IO (Decode16,
-				0x0CF8,             // Address Range Minimum
-				0x0CF8,             // Address Range Maximum
-				0x01,               // Address Alignment
-				0x08,               // Address Length
-				)
-				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-				0x0000,             // Address Space Granularity
-				0x0000,             // Address Range Minimum
-				0x0CF7,             // Address Range Maximum
-				0x0000,             // Address Translation Offset
-				0x0CF8,             // Address Length
-				,, , TypeStatic)
-			    })
-				/* Methods bellow use SSDT to get actual MMIO regs
-				   The IO ports are from 0xd00, optionally an VGA,
-				   otherwise the info from MMIO is used.
-				 */
-				Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
-				Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
-				Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
-				Return (Local3)
-			}
-
-		} /* End Device(PCI0)  */
-
-	} /* End \_SB scope */
-}
-/* End of ASL file */
diff --git a/src/mainboard/asrock/939a785gmh/get_bus_conf.c b/src/mainboard/asrock/939a785gmh/get_bus_conf.c
deleted file mode 100644
index 64b3ed7032..0000000000
--- a/src/mainboard/asrock/939a785gmh/get_bus_conf.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/multicore.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
-u8 bus_rs780[11];
-u8 bus_sb700[2];
-u32 apicid_sb700;
-
-/*
-* Here you only need to set value in pci1234 for HT-IO that could be installed or not
-* You may need to preset pci1234 for HTIO board,
-* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
-*/
-u32 pci1234x[] = {
-	0x0000ff0,
-};
-
-/*
-* HT Chain device num, actually it is unit id base of every ht device in chain,
-* assume every chain only have 4 ht device at most
-*/
-u32 hcdnx[] = {
-	0x20202020,
-};
-
-u32 sbdn_rs780;
-u32 sbdn_sb700;
-
-
-
-static u32 get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
-	u32 apicid_base;
-	struct device *dev;
-	int i;
-
-	if (get_bus_conf_done == 1)
-		return;		/* do it only once */
-	get_bus_conf_done = 1;
-
-	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
-	for (i = 0; i < sysconf.hc_possible_num; i++) {
-		sysconf.pci1234[i] = pci1234x[i];
-		sysconf.hcdn[i] = hcdnx[i];
-	}
-
-	get_sblk_pci1234();
-
-	sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
-	sbdn_rs780 = sysconf.sbdn;
-	sbdn_sb700 = 0;
-
-	for (i = 0; i < 2; i++) {
-		bus_sb700[i] = 0;
-	}
-	for (i = 0; i < ARRAY_SIZE(bus_rs780); i++) {
-		bus_rs780[i] = 0;
-	}
-
-	bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
-	bus_sb700[0] = bus_rs780[0];
-
-	/* sb700 */
-	dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4));
-	if (dev) {
-		bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-	}
-
-	/* rs780 */
-	for (i = 1; i < ARRAY_SIZE(bus_rs780); i++) {
-		dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
-		if (dev) {
-			bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-		}
-	}
-
-	/* I/O APICs:   APIC ID Version State   Address */
-	if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
-		apicid_base = get_apicid_base(1);
-	else
-		apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
-	apicid_sb700 = apicid_base + 0;
-}
diff --git a/src/mainboard/asrock/939a785gmh/irq_tables.c b/src/mainboard/asrock/939a785gmh/irq_tables.c
deleted file mode 100644
index ef2a3ec45c..0000000000
--- a/src/mainboard/asrock/939a785gmh/irq_tables.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-extern u8 bus_rs780[8];
-extern u8 bus_sb700[2];
-extern unsigned long sbdn_sb700;
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	get_bus_conf();		/* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
-
-	/* Align the table to be 16 byte aligned. */
-	addr += 15;
-	addr &= ~15;
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *) (addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = bus_sb700[0];
-	pirq->rtr_devfn = ((sbdn_sb700 + 0x14) << 3) | 4;
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* pci bridge */
-	write_pirq_info(pirq_info, bus_sb700[0], ((sbdn_sb700 + 0x14) << 3) | 4,
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
-			0);
-	pirq_info++;
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-	if (sum != pirq->checksum) {
-		pirq->checksum = sum;
-	}
-
-	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
-
-	return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c
deleted file mode 100644
index 85d9060c5e..0000000000
--- a/src/mainboard/asrock/939a785gmh/mainboard.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/pci_def.h>
-#include "southbridge/amd/sb700/sb700.h"
-#include "southbridge/amd/sb700/smbus.h"
-
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
-u8 is_dev3_present(void);
-
-static void pcie_rst_toggle(u8 val) {
-	u8 byte;
-
-	byte = pm_ioread(0x8d);
-	byte &= ~(3 << 1);
-	pm_iowrite(0x8d, byte);
-
-	byte = pm_ioread(0x94);
-	/* Output enable */
-	byte &= ~(3 << 2);
-	/* Toggle GPM8, GPM9 */
-	byte &= ~(3 << 0);
-	byte |= val;
-	pm_iowrite(0x94, byte);
-}
-
-void set_pcie_dereset()
-{
-    pcie_rst_toggle(0x3);
-}
-
-void set_pcie_reset()
-{
-    pcie_rst_toggle(0x0);
-}
-
-#if 0	     /* not tested yet */
-/********************************************************
-* mahogany uses SB700 GPIO9 to detect IDE_DMA66.
-* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
-* get the cable type, 40 pin or 80 pin?
-********************************************************/
-static void get_ide_dma66(void)
-{
-	u8 byte;
-	/*u32 sm_dev, ide_dev; */
-	struct device *sm_dev, ide_dev;
-
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
-	byte = pci_read_config8(sm_dev, 0xA9);
-	byte |= (1 << 5);	/* Set Gpio9 as input */
-	pci_write_config8(sm_dev, 0xA9, byte);
-
-	ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
-	byte = pci_read_config8(ide_dev, 0x56);
-	byte &= ~(7 << 0);
-	if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
-		byte |= 2 << 0;	/* mode 2 */
-	else
-		byte |= 5 << 0;	/* mode 5 */
-	pci_write_config8(ide_dev, 0x56, byte);
-}
-#endif	/* get_ide_dma66 */
-
-u8 is_dev3_present(void)
-{
-	return 0;
-}
-
-/*************************************************
-* enable the dedicated function in mahogany board.
-* This function called early than rs780_enable.
-*************************************************/
-static void mainboard_enable(struct device *dev)
-{
-	printk(BIOS_INFO, "Mainboard 939A785GMH/128M Enable. dev=0x%p\n", dev);
-
-	set_pcie_dereset();
-	/* get_ide_dma66(); */
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
-
-/* override the default SATA PHY setup */
-void sb7xx_51xx_setup_sata_phys(struct device *dev) {
-	/* RPR7.6.1 Program the PHY Global Control to 0x2C00 */
-	pci_write_config16(dev, 0x86, 0x2c00);
-
-	/* RPR7.6.2 SATA GENI PHY ports setting */
-	pci_write_config32(dev, 0x88, 0x01B48016);
-	pci_write_config32(dev, 0x8c, 0x01B48016);
-	pci_write_config32(dev, 0x90, 0x01B48016);
-	pci_write_config32(dev, 0x94, 0x01B48016);
-	pci_write_config32(dev, 0x98, 0x01B48016);
-	pci_write_config32(dev, 0x9C, 0x01B48016);
-
-	/* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */
-	pci_write_config16(dev, 0xA0, 0xA07A);
-	pci_write_config16(dev, 0xA2, 0xA07A);
-	pci_write_config16(dev, 0xA4, 0xA07A);
-	pci_write_config16(dev, 0xA6, 0xA07A);
-	pci_write_config16(dev, 0xA8, 0xA07A);
-	pci_write_config16(dev, 0xAA, 0xA0FF);
-}
diff --git a/src/mainboard/asrock/939a785gmh/mptable.c b/src/mainboard/asrock/939a785gmh/mptable.c
deleted file mode 100644
index fe104d031f..0000000000
--- a/src/mainboard/asrock/939a785gmh/mptable.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <arch/io.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern u8 bus_rs780[11];
-extern u8 bus_sb700[2];
-
-extern u32 apicid_sb700;
-
-extern u32 sbdn_rs780;
-extern u32 sbdn_sb700;
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	int bus_isa;
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-	smp_write_processors(mc);
-
-	get_bus_conf();
-
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-	/* I/O APICs:   APIC ID Version State   Address */
-	{
-		struct device *dev;
-		u32 dword;
-		u8 byte;
-
-		dev =
-		    dev_find_slot(bus_sb700[0],
-				  PCI_DEVFN(sbdn_sb700 + 0x14, 0));
-		if (dev) {
-			dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
-			smp_write_ioapic(mc, apicid_sb700,
-					 0x11,(void *) dword);
-
-			/* Initialize interrupt mapping */
-			/* aza */
-			byte = pci_read_config8(dev, 0x63);
-			byte &= 0xf8;
-			byte |= 0;	/* 0: INTA, ...., 7: INTH */
-			pci_write_config8(dev, 0x63, byte);
-
-			/* SATA */
-			dword = pci_read_config32(dev, 0xac);
-			dword &= ~(7 << 26);
-			dword |= 6 << 26;	/* 0: INTA, ...., 7: INTH */
-			/* dword |= 1 << 22; PIC and APIC co exists */
-			pci_write_config32(dev, 0xac, dword);
-
-			/*
-			 * 00:12.0: PROG SATA : INT F
-			 * 00:13.0: INTA USB_0
-			 * 00:13.1: INTB USB_1
-			 * 00:13.2: INTC USB_2
-			 * 00:13.3: INTD USB_3
-			 * 00:13.4: INTC USB_4
-			 * 00:13.5: INTD USB2
-			 * 00:14.1: INTA IDE
-			 * 00:14.2: Prog HDA : INT E
-			 * 00:14.5: INTB ACI
-			 * 00:14.6: INTB MCI
-			 */
-		}
-	}
-
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
-	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
-	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
-
-	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
-	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);
-	return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asrock/939a785gmh/resourcemap.c b/src/mainboard/asrock/939a785gmh/resourcemap.c
deleted file mode 100644
index 0f1d4cb6e6..0000000000
--- a/src/mainboard/asrock/939a785gmh/resourcemap.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-static void setup_939a785gmh_resource_map(void)
-{
-	static const unsigned int register_values[] = {
-		/* Careful set limit registers before base registers which contain the enables */
-		/* DRAM Limit i Registers
-		* F1:0x44 i = 0
-		* F1:0x4C i = 1
-		* F1:0x54 i = 2
-		* F1:0x5C i = 3
-		* F1:0x64 i = 4
-		* F1:0x6C i = 5
-		* F1:0x74 i = 6
-		* F1:0x7C i = 7
-		* [ 2: 0] Destination Node ID
-		*	000 = Node 0
-		*	001 = Node 1
-		*	010 = Node 2
-		*	011 = Node 3
-		*	100 = Node 4
-		*	101 = Node 5
-		*	110 = Node 6
-		*	111 = Node 7
-		* [ 7: 3] Reserved
-		* [10: 8] Interleave select
-		*	specifies the values of A[14:12] to use with interleave enable.
-		* [15:11] Reserved
-		* [31:16] DRAM Limit Address i Bits 39-24
-		*	This field defines the upper address bits of a 40 bit  address
-		*	that define the end of the DRAM region.
-		*/
-		PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
-		PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
-		PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
-		PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
-		PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
-		PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
-		PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
-		/* DRAM Base i Registers
-		* F1:0x40 i = 0
-		* F1:0x48 i = 1
-		* F1:0x50 i = 2
-		* F1:0x58 i = 3
-		* F1:0x60 i = 4
-		* F1:0x68 i = 5
-		* F1:0x70 i = 6
-		* F1:0x78 i = 7
-		* [ 0: 0] Read Enable
-		*	0 = Reads Disabled
-		*	1 = Reads Enabled
-		* [ 1: 1] Write Enable
-		*	0 = Writes Disabled
-		*	1 = Writes Enabled
-		* [ 7: 2] Reserved
-		* [10: 8] Interleave Enable
-		*	000 = No interleave
-		*	001 = Interleave on A[12] (2 nodes)
-		*	010 = reserved
-		*	011 = Interleave on A[12] and A[14] (4 nodes)
-		*	100 = reserved
-		*	101 = reserved
-		*	110 = reserved
-		*	111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
-		* [15:11] Reserved
-		* [13:16] DRAM Base Address i Bits 39-24
-		*	This field defines the upper address bits of a 40-bit address
-		*	that define the start of the DRAM region.
-		*/
-		PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
-		/* Memory-Mapped I/O Limit i Registers
-		 * F1:0x84 i = 0
-		 * F1:0x8C i = 1
-		 * F1:0x94 i = 2
-		 * F1:0x9C i = 3
-		 * F1:0xA4 i = 4
-		 * F1:0xAC i = 5
-		 * F1:0xB4 i = 6
-		 * F1:0xBC i = 7
-		 * [ 2: 0] Destination Node ID
-		 *	000 = Node 0
-		 *	001 = Node 1
-		 *	010 = Node 2
-		 *	011 = Node 3
-		 *	100 = Node 4
-		 *	101 = Node 5
-		 *	110 = Node 6
-		 *	111 = Node 7
-		 * [ 3: 3] Reserved
-		 * [ 5: 4] Destination Link ID
-		 *	00 = Link 0
-		 *	01 = Link 1
-		 *	10 = Link 2
-		 *	11 = Reserved
-		 * [ 6: 6] Reserved
-		 * [ 7: 7] Non-Posted
-		 *	0 = CPU writes may be posted
-		 *	1 = CPU writes must be non-posted
-		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
-		 *	This field defines the upp adddress bits of a 40-bit address that
-		 *	defines the end of a memory-mapped I/O region n
-		 */
-		PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
-		/* Memory-Mapped I/O Base i Registers
-		* F1:0x80 i = 0
-		* F1:0x88 i = 1
-		* F1:0x90 i = 2
-		* F1:0x98 i = 3
-		* F1:0xA0 i = 4
-		* F1:0xA8 i = 5
-		* F1:0xB0 i = 6
-		* F1:0xB8 i = 7
-		* [ 0: 0] Read Enable
-		*	0 = Reads disabled
-		*	1 = Reads Enabled
-		* [ 1: 1] Write Enable
-		*	0 = Writes disabled
-		*	1 = Writes Enabled
-		* [ 2: 2] Cpu Disable
-		*	0 = Cpu can use this I/O range
-		*	1 = Cpu requests do not use this I/O range
-		* [ 3: 3] Lock
-		*	0 = base/limit registers i are read/write
-		*	1 = base/limit registers i are read-only
-		* [ 7: 4] Reserved
-		* [31: 8] Memory-Mapped I/O Base Address i (39-16)
-		*	This field defines the upper address bits of a 40bit address
-		*	that defines the start of memory-mapped I/O region i
-		*/
-		PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
-		/* PCI I/O Limit i Registers
-		* F1:0xC4 i = 0
-		* F1:0xCC i = 1
-		* F1:0xD4 i = 2
-		* F1:0xDC i = 3
-		* [ 2: 0] Destination Node ID
-		*	000 = Node 0
-		*	001 = Node 1
-		*	010 = Node 2
-		*	011 = Node 3
-		*	100 = Node 4
-		*	101 = Node 5
-		*	110 = Node 6
-		*	111 = Node 7
-		* [ 3: 3] Reserved
-		* [ 5: 4] Destination Link ID
-		*	00 = Link 0
-		*	01 = Link 1
-		*	10 = Link 2
-		*	11 = reserved
-		* [11: 6] Reserved
-		* [24:12] PCI I/O Limit Address i
-		*	This field defines the end of PCI I/O region n
-		* [31:25] Reserved
-		*/
-		PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
-		PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
-		/* PCI I/O Base i Registers
-		 * F1:0xC0 i = 0
-		 * F1:0xC8 i = 1
-		 * F1:0xD0 i = 2
-		 * F1:0xD8 i = 3
-		 * [ 0: 0] Read Enable
-		 *	0 = Reads Disabled
-		 *	1 = Reads Enabled
-		 * [ 1: 1] Write Enable
-		 *	0 = Writes Disabled
-		 *	1 = Writes Enabled
-		 * [ 3: 2] Reserved
-		 * [ 4: 4] VGA Enable
-		 *	0 = VGA matches Disabled
-		 *	1 = matches all address < 64K and where A[9:0] is in the
-		 *	range 3B0-3BB or 3C0-3DF independen of the base & limit registers
-		 * [ 5: 5] ISA Enable
-		 *	0 = ISA matches Disabled
-		 *	1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
-		 *	from matching agains this base/limit pair
-		 * [11: 6] Reserved
-		 * [24:12] PCI I/O Base i
-		 *	This field defines the start of PCI I/O region n
-		 * [31:25] Reserved
-		 */
-		PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
-		PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
-		/* Config Base and Limit i Registers
-		 * F1:0xE0 i = 0
-		 * F1:0xE4 i = 1
-		 * F1:0xE8 i = 2
-		 * F1:0xEC i = 3
-		 * [ 0: 0] Read Enable
-		 *	0 = Reads Disabled
-		 *	1 = Reads Enabled
-		 * [ 1: 1] Write Enable
-		 *	0 = Writes Disabled
-		 *	1 = Writes Enabled
-		 * [ 2: 2] Device Number Compare Enable
-		 *	0 = The ranges are based on bus number
-		 *	1 = The ranges are ranges of devices on bus 0
-		 * [ 3: 3] Reserved
-		 * [ 6: 4] Destination Node
-		 *	000 = Node 0
-		 *	001 = Node 1
-		 *	010 = Node 2
-		 *	011 = Node 3
-		 *	100 = Node 4
-		 *	101 = Node 5
-		 *	110 = Node 6
-		 *	111 = Node 7
-		 * [ 7: 7] Reserved
-		 * [ 9: 8] Destination Link
-		 *	00 = Link 0
-		 *	01 = Link 1
-		 *	10 = Link 2
-		 *	11 - Reserved
-		 * [15:10] Reserved
-		 * [23:16] Bus Number Base i
-		 *	This field defines the lowest bus number in configuration region i
-		 * [31:24] Bus Number Limit i
-		 *	This field defines the highest bus number in configuration regin i
-		 */
-		PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003,
-		PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
-		PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
-	};
-
-	int max;
-	max = ARRAY_SIZE(register_values);
-	setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
deleted file mode 100644
index d6a85ccee8..0000000000
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- * Copyright (C) 2010 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <spd.h>
-#include <cpu/x86/lapic.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627dhg/w83627dhg.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include <southbridge/amd/sb700/sb700.h>
-#include <southbridge/amd/sb700/smbus.h>
-#include <northbridge/amd/amdk8/pre_f.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
-#define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
-
-unsigned get_sbdn(unsigned bus);
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(u32 device, u32 address)
-{
-	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
-
-#include <southbridge/amd/rs780/rs780.h>
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "northbridge/amd/amdk8/raminit.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-static void sio_init(void)
-{
-	u8 reg;
-
-	pnp_enter_ext_func_mode(GPIO2345_DEV);
-	pnp_set_logical_device(GPIO2345_DEV);
-
-	/* Pin 119 ~ 120 is GP21, GP20  */
-	reg = pnp_read_config(GPIO2345_DEV, 0x29);
-	pnp_write_config(GPIO2345_DEV, 0x29, (reg | 2));
-
-	/* Turn on the Power LED ("Suspend LED" in Super I/O) */
-	reg = pnp_read_config(GPIO2345_DEV, 0xf3);
-	pnp_write_config(GPIO2345_DEV, 0xf3, (reg | 0x40));
-
-	/* todo document this */
-	pnp_write_config(GPIO2345_DEV, 0x2c, 0x1);
-	pnp_write_config(GPIO2345_DEV, 0x2d, 0x1);
-
-	/* GPO20 - sideport voltage 1 = 1.82 0 = 1.92
-	   GPI21 - unknown input (NC?)
-	   GPI22 - unknown input (NC?)
-	   GPO23 - mgpuV bit0
-	   GP24-27 - PS/2 mouse/keyb (only keyb is connected use flip interface for mouse)
-	*/
-	pnp_write_config(GPIO2345_DEV, 0x30, 0x07);	/* Enable GPIO 2,3,4. */
-	pnp_write_config(GPIO2345_DEV, 0xe3, 0xf6);	/* dir of GPIO2 11110110*/
-	pnp_write_config(GPIO2345_DEV, 0xe4, 0x0e);	/* data */
-	pnp_write_config(GPIO2345_DEV, 0xe5, 0x00);	/* No inversion */
-
-	/* GPIO30 - unknown output, set to 0
-	   GPI31 - unknown input NC?
-	   GPI32 - unknown input NC?
-	   GPIO33 - unknown output, set to 0.
-	   GPI34 - unknown input NC?
-	   GPO35 - loadline control 1 = enabled (2 phase clock) 0 = disabled 4 phase clock
-	   GPIO36 - input = HT voltage 1.30V output (low) = HT voltage 1.35V
-	   GP37 - unknown input NC? */
-
-	pnp_write_config(GPIO2345_DEV, 0xf0, 0xd6);	/* dir of GPIO3 11010110*/
-	pnp_write_config(GPIO2345_DEV, 0xf1, 0x96);	/* data */
-	pnp_write_config(GPIO2345_DEV, 0xf2, 0x00);	/* No inversion */
-
-	/* GPO40 - mgpuV bit2
-	   GPO41 - mgpuV bit1
-	   GPO42  - IRTX
-	   GPO43  - IRRX
-	   GPIO44 - memory voltage bit2 (input/outputlow)
-	   GPIO45 - memory voltage bit1 (2.60 (000) - 2.95 (111))
-	   GPIO46 - memory voltage bit0
-	   GPIO47 - unknown input? */
-
-	pnp_write_config(GPIO2345_DEV, 0xf4, 0xd0);	/* dir of GPIO4 11010000 */
-	pnp_write_config(GPIO2345_DEV, 0xf5, 0x83);	/* data */
-	pnp_write_config(GPIO2345_DEV, 0xf6, 0x00);	/* No inversion */
-
-	pnp_write_config(GPIO2345_DEV, 0xf7, 0x00);	/* MFC */
-	pnp_write_config(GPIO2345_DEV, 0xf8, 0x00);	/* MFC */
-	pnp_write_config(GPIO2345_DEV, 0xfe, 0x07);	/* trig type */
-	pnp_exit_ext_func_mode(GPIO2345_DEV);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	static const u16 spd_addr[] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
-	int needs_reset = 0;
-	u32 bsp_apicid = 0;
-	msr_t msr;
-	struct cpuid_result cpuid1;
-	struct sys_info *sysinfo = &sysinfo_car;
-
-	if (!cpu_init_detectedx && boot_cpu()) {
-		/* Nothing special needs to be done to find bus 0 */
-		/* Allow the HT devices to be found */
-		enumerate_ht_chain();
-		/* sb7xx_51xx_lpc_port80(); */
-		sb7xx_51xx_pci_port80();
-	}
-
-	if (bist == 0)
-		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
-	enable_rs780_dev8();
-	sb7xx_51xx_lpc_init();
-
-	sio_init();
-	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-	printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
-
-	setup_939a785gmh_resource_map();
-
-	setup_coherent_ht_domain();
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
-	/* It is said that we should start core1 after all core0 launched */
-	wait_all_core0_started();
-	start_other_cores();
-#endif
-	wait_all_aps_started(bsp_apicid);
-
-	ht_setup_chains_x(sysinfo);
-
-	/* run _early_setup before soft-reset. */
-	rs780_early_setup();
-	sb7xx_51xx_early_setup();
-
-	/* Check to see if processor is capable of changing FIDVID  */
-	/* otherwise it will throw a GP# when reading FIDVID_STATUS */
-	cpuid1 = cpuid(0x80000007);
-	if ((cpuid1.edx & 0x6) == 0x6) {
-		/* Read FIDVID_STATUS */
-		msr = rdmsr(0xc0010042);
-		printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
-		enable_fid_change();
-		enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-		init_fidvid_bsp(bsp_apicid);
-
-		/* show final fid and vid */
-		msr = rdmsr(0xc0010042);
-		printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-	} else {
-		printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
-	}
-
-	needs_reset = optimize_link_coherent_ht();
-	needs_reset |= optimize_link_incoherent_ht(sysinfo);
-	rs780_htinit();
-	printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
-
-	if (needs_reset) {
-		printk(BIOS_INFO, "ht reset -\n");
-		soft_reset();
-	}
-
-	allow_all_aps_stop(bsp_apicid);
-
-	/* It's the time to set ctrl now; */
-	printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
-		     sysinfo->nodes, sysinfo->ctrl, spd_addr);
-	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-
-	sb7xx_51xx_before_pci_init();
-}