diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-20 07:45:17 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-12-01 05:46:54 +0100 |
| commit | 036a581b8fa9478d4dba1bf9e576ee9cc0bead24 (patch) | |
| tree | 9b57756ad8ae88cb6287c43f9fcd351b55bace0e /src/mainboard/asrock | |
| parent | f08c8a5c2d34383ddadcf66a7e5c044907280fec (diff) | |
AGESA f14: Consolidate XIP cache
Do this like fam15tn to reduce code duplication.
Change-Id: I064fd27b85be7fb0c9d6918a84fc6f9b17065534
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17563
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/asrock')
| -rw-r--r-- | src/mainboard/asrock/e350m1/romstage.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 50f3f6b56a..6d2cad2b73 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -43,13 +43,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* - * All cores: allow caching of flash chip code and data - * (there are no cache-as-ram reliability concerns with family 14h) - */ - __writemsr(0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); - __writemsr(0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr(0xc0010062, 0); |