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authorEvan Green <evgreen@chromium.org>2019-03-18 09:08:00 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-03-22 12:17:37 +0000
commit9c8044bdcd2aa77d8a8092b270ca36fd3aa23b87 (patch)
treeb6b499f301ec001852f214977b644bd097d5a5c8 /src/mainboard/asrock
parent0146bce26252fa9e959c083fd69c8f667746de86 (diff)
mb/google/hatch: Add SX9310 SAR0 sensor
Add SAR0, which is an SX9310. The schematics and layout have a second SAR1 sensor provisioned on I2C4, with an interrupt of GPP_A6, but this is not populated. Signed-off-by: Evan Green <evgreen@chromium.org> BUG=b:128540461 BRANCH=none TEST=Boot kernel with sx9310 driver, see it come up happily Change-Id: I63943cc7da5ff56f6ef6dcbd99bb8f8f031e8bf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/31998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Enrico Granata <egranata@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
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