diff options
author | Marc Jones <marcj303@gmail.com> | 2012-01-17 16:51:24 -0700 |
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committer | Marc Jones <marcj303@gmail.com> | 2012-01-18 23:09:17 +0100 |
commit | 938ae3ed18ac72878e572e4cdc2ff5029fe97d74 (patch) | |
tree | a451e7f867913e4bb4d57238dd77c4456ba6c993 /src/mainboard/asrock | |
parent | 0f1dc4eb5bb9941bdb8ff833ec745e1cfeaa9d28 (diff) |
Clean up AMD romstage.c serial output
This cleans up the strings in romstage.c, removing the ugly "got past".
Also, cleaned up comments and some spacing.
Change-Id: I0124df76eb442f8a0009a31a8632e4fd67ed7782
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/539
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/asrock')
-rw-r--r-- | src/mainboard/asrock/e350m1/romstage.c | 60 |
1 files changed, 33 insertions, 27 deletions
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 133aca7350..8b46b19e8d 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -47,12 +47,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; u8 reg8; - // all cores: allow caching of flash chip code and data - // (there are no cache-as-ram reliability concerns with family 14h) + /* + * All cores: allow caching of flash chip code and data + * (there are no cache-as-ram reliability concerns with family 14h) + */ __writemsr(0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); __writemsr(0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); - // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time + /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr(0xc0010062, 0); if (!cpu_init_detectedx && boot_cpu()) { @@ -68,47 +70,50 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x34); report_bist_failure(bist); - // Load MPB + /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x35); + printk(BIOS_DEBUG, "agesawrapper_amdinitmmio "); val = agesawrapper_amdinitmmio(); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x37); + printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); val = agesawrapper_amdinitreset(); - if (val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", - val); - } - - post_code(0x38); - printk(BIOS_DEBUG, "Got past sb800_early_setup\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x39); + printk(BIOS_DEBUG, "agesawrapper_amdinitearly "); val = agesawrapper_amdinitearly(); - if (val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", - val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x40); + printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); val = agesawrapper_amdinitpost(); - if (val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", - val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); post_code(0x41); + printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); val = agesawrapper_amdinitenv(); - if (val) { - printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", - val); - } - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); /* Initialize i8259 pic */ post_code(0x41); @@ -120,6 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x50); copy_and_run(0); + printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); - post_code(0x54); // Should never see this post code. + post_code(0x54); /* Should never see this post code. */ } |