diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2022-11-29 17:36:51 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-02 14:39:56 +0000 |
| commit | dc3beea75d3050600842112cfd7fd48baa65278d (patch) | |
| tree | ca9839a61c90cc7b972650c0eb1a2e92a6a25eb9 /src/mainboard/asrock | |
| parent | 87a98b55b2466638587ea44fc7eaa13d93525656 (diff) | |
sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary}
Change-Id: Ia71692ecf74fd8921eeafabac9a4cb862da90e81
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70114
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/asrock')
5 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index 5d10628a62..846a02b676 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -38,7 +38,7 @@ chip northbridge/intel/x4x # Northbridge # 2 SCI (if corresponding GPIO_EN bit is also set) register "gpi13_routing" = "2" - register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb index d0759e2346..8115430cd6 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb @@ -33,7 +33,7 @@ chip northbridge/intel/x4x # Northbridge register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x0b" - register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "gpe0_en" = "0x440" register "gen1_dec" = "0x000c0291" # Superio HWM diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index 818ceaa5c0..ef019d1ac2 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -33,7 +33,7 @@ chip northbridge/intel/x4x # Northbridge register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x0b" - register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb index 9f4142bf5d..4237041af7 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb @@ -31,7 +31,7 @@ chip northbridge/intel/x4x # Northbridge register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x0b" - register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb index e0df76be96..23268f2bdf 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb @@ -33,7 +33,7 @@ chip northbridge/intel/x4x # Northbridge register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x0b" - register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "gpe0_en" = "0x440" register "gen1_dec" = "0x000c0291" # Superio HWM |