diff options
| author | Himanshu Sahdev <himanshu.sahdev@intel.com> | 2022-09-27 13:47:08 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-30 17:58:47 +0000 |
| commit | 542ac2f3f869f75a2b4c9f8b9d1953a94975e497 (patch) | |
| tree | 5a824bba0d169c702e84e613d2d2ffaa26a47b79 /src/mainboard/asrock | |
| parent | 2ddcf409c3b79672665163e7a826991779dd620e (diff) | |
guybrush: mark RO_GSCVD area unused
This area relates to storing of AP RO verification information.
CONFIG_VBOOT_GSCVD is enabled by default for TPM_GOOGLE_TI50 and
guybrush is using TPM_GOOGLE_CR50.
Signed PSP verstage has the FMAP embedded. Since CB:67376 shifted the
RO section up by 8K, they were misaligned. Hence marking this area as
unused instead of removing the same to work around ChromeOS
infrastructure shortcoming.
Signed-off-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Change-Id: Id852e5b5c1f777992a96a75143757f4df8d975b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67901
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asrock')
0 files changed, 0 insertions, 0 deletions