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| author | Tracy Wu <tracy.wu@intel.corp-partner.google.com> | 2022-12-22 16:28:15 +0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-12-24 23:36:59 +0000 |
| commit | 387ec919d9f74947b84ed08d5eece8b2f0ca9cae (patch) | |
| tree | 606fd990c01b09ed306b5c24548d59f25a28aa7d /src/mainboard/asrock | |
| parent | 2a12b6a9a40616e9844e45b3afc4acc8befd69db (diff) | |
soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATE
With enabling FSP Notify Phase APIs, it has chance to issue a global
reset in FSP after CSE EOP (with selecting SOC_INTEL_CSE_SEND_EOP_EARLY
), which CSE already in idle mode and cause failure. For this reason we
should drop SOC_INTEL_CSE_SEND_EOP_EARLY in all ADL sku and select
SOC_INTEL_CSE_SEND_EOP_LATE instead.
BUG=b:261544011
BRANCH=firmware-brya-14505.B
TEST=tested and verified on Marasov, make sure this kind of global
reset can be executed successfully.
Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Change-Id: I29736ca8efee64dd03feb48404241ee6295b7c72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard/asrock')
0 files changed, 0 insertions, 0 deletions