diff options
author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-03-03 08:45:19 +0200 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-03-04 15:58:55 +0000 |
commit | 3855c01e0a9d9e9787652479576e882bcda9fde5 (patch) | |
tree | 940945c52e59fb334b41960ab17513f240e95884 /src/mainboard/asrock | |
parent | 369559379453f9bf0e917635b642e6f70d55a93e (diff) |
device/pnp: Add header files for PNP ops
Change-Id: Ifda495420cfb121ad32920bb9f1cbdeef41f6d3a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31698
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asrock')
-rw-r--r-- | src/mainboard/asrock/b75pro3-m/romstage.c | 1 | ||||
-rw-r--r-- | src/mainboard/asrock/g41c-gs/romstage.c | 2 | ||||
-rw-r--r-- | src/mainboard/asrock/h81m-hds/romstage.c | 1 |
3 files changed, 3 insertions, 1 deletions
diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/romstage.c index 205c08c0f1..51991248af 100644 --- a/src/mainboard/asrock/b75pro3-m/romstage.c +++ b/src/mainboard/asrock/b75pro3-m/romstage.c @@ -15,6 +15,7 @@ */ #include <device/pci_ops.h> +#include <device/pnp_ops.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <superio/nuvoton/nct6776/nct6776.h> #include <superio/nuvoton/common/nuvoton.h> diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index 12f5cd4ffd..8474d189a3 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -15,7 +15,7 @@ * GNU General Public License for more details. */ -#include <arch/io.h> +#include <device/pnp_ops.h> #include <device/pci_ops.h> #include <console/console.h> #include <cpu/intel/romstage.h> diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index c6bef9f0b4..78eb65785e 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -18,6 +18,7 @@ #include <stdint.h> #include <cpu/intel/romstage.h> #include <cpu/intel/haswell/haswell.h> +#include <device/pnp_ops.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/pei_data.h> #include <southbridge/intel/common/gpio.h> |