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authorAngel Pons <th3fanbus@gmail.com>2020-07-25 13:44:34 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-26 21:45:12 +0000
commit4276050d13cb8c555f0375d4ec44d33ab5d58402 (patch)
treec07e6d46c94c5bb055e41b5b7dfe708423543300 /src/mainboard/asrock
parent7417bb0e5a8bddbf9a56b990119fa3af56e663ac (diff)
mb/*/*/devicetree.cb: Normalize disabled PIRQ values
If bit 7 of a PIRQ route is set, it is disabled. Modern OSes don't use PIRQ routing, so we might as well zero the other bits for consistency. Tested on Asrock B85M Pro4 with SeaBIOS 1.13.0, still boots. Change-Id: I78980b9ea5e878a6200df0f6c18c5e7d06a7950a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43861 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asrock')
-rw-r--r--src/mainboard/asrock/b85m_pro4/devicetree.cb12
-rw-r--r--src/mainboard/asrock/h81m-hds/devicetree.cb8
2 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb
index a044d0a8a3..b724652ea6 100644
--- a/src/mainboard/asrock/b85m_pro4/devicetree.cb
+++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb
@@ -27,14 +27,14 @@ chip northbridge/intel/haswell
chip southbridge/intel/lynxpoint
register "gen1_dec" = "0x000c0291" # Super I/O HWM
- register "pirqa_routing" = "0x8b"
+ register "pirqa_routing" = "0x80"
register "pirqb_routing" = "0x80"
- register "pirqc_routing" = "0x83"
- register "pirqd_routing" = "0x8a"
- register "pirqe_routing" = "0x83"
+ register "pirqc_routing" = "0x80"
+ register "pirqd_routing" = "0x80"
+ register "pirqe_routing" = "0x80"
register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x8b"
- register "pirqh_routing" = "0x8a"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x80"
register "sata_ahci" = "1"
register "sata_port_map" = "0x3f"
diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb
index f08d2d560f..561c1e35d5 100644
--- a/src/mainboard/asrock/h81m-hds/devicetree.cb
+++ b/src/mainboard/asrock/h81m-hds/devicetree.cb
@@ -35,14 +35,14 @@ chip northbridge/intel/haswell
end
chip southbridge/intel/lynxpoint
- register "pirqa_routing" = "0x8b"
+ register "pirqa_routing" = "0x80"
register "pirqb_routing" = "0x80"
- register "pirqc_routing" = "0x8b"
- register "pirqd_routing" = "0x8a"
+ register "pirqc_routing" = "0x80"
+ register "pirqd_routing" = "0x80"
register "pirqe_routing" = "0x80"
register "pirqf_routing" = "0x80"
register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x8a"
+ register "pirqh_routing" = "0x80"
register "sata_ahci" = "1"
register "sata_port_map" = "0x33"