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authorPaul Menzel <paulepanter@users.sourceforge.net>2013-02-23 00:15:49 +0100
committerMarc Jones <marc.jones@se-eng.com>2013-03-07 00:45:41 +0100
commite988b515f11fa9483fc5209a9894b8d485525a61 (patch)
treec732273dbe9dd9cd5baa79225d2da7ad9a985873 /src/mainboard/asrock
parent6bde149d9c56a824eff5db7bb06d7c386fb2be30 (diff)
ASRock E350M1: Let `BiosGnbPcieSlotReset()` return `AGESA_UNSUPPORTED`
Quoting Jens Rottmann [1]: Nevertheless I still think this whole function is bogus for the E350M1. The function assumes GPIO21 is wired to reset APU PCIe lane 0+1 (PCIe x8, port 4+5 as Coreboot/AGESA calls it), GPIO25 resets lane 2 (PCIe x4) and GPIO02 lane 3. But the E350M1 has PCIe x16 i.e. probably APU lanes 0-3 bundled, completely different layout. They could have chosen GPIO21 to force resets, or 25 - or maybe 50 like on the Persimmon or any other they fancied or - and this is the most probable - none at all. Having BiosGnbPcieSlotReset() toggle some GPIOs without knowing what they do on the E350M1 (if anything at all) is nonsense. In my opinion this whole function should just "return AGESA_UNSUPPORTED" and good riddance. [1] http://review.coreboot.org/#/c/2445/ Change-Id: Iac66da41182e838c7e6925250cc3982adbb3e4ec Reported-by: Jens Rottmann <JRottmann@LiPPERTembedded.de> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2489 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Diffstat (limited to 'src/mainboard/asrock')
-rw-r--r--src/mainboard/asrock/e350m1/BiosCallOuts.c77
-rw-r--r--src/mainboard/asrock/e350m1/BiosCallOuts.h9
-rw-r--r--src/mainboard/asrock/e350m1/PlatformGnbPcie.c8
3 files changed, 6 insertions, 88 deletions
diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c
index 1f1aa06094..fc5b91fa9c 100644
--- a/src/mainboard/asrock/e350m1/BiosCallOuts.c
+++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c
@@ -525,80 +525,5 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *Conf
/* PCIE slot reset control */
AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
- AGESA_STATUS Status;
- UINTN FcnData;
- PCIe_SLOT_RESET_INFO *ResetInfo;
-
- UINT32 GpioMmioAddr;
- UINT32 AcpiMmioAddr;
- UINT8 Data8;
- UINT16 Data16;
-
- FcnData = Data;
- ResetInfo = ConfigPtr;
- // Get SB800 MMIO Base (AcpiMmioAddr)
- WriteIo8(0xCD6, 0x27);
- Data8 = ReadIo8(0xCD7);
- Data16=Data8<<8;
- WriteIo8(0xCD6, 0x26);
- Data8 = ReadIo8(0xCD7);
- Data16|=Data8;
- AcpiMmioAddr = (UINT32)Data16 << 16;
- Status = AGESA_UNSUPPORTED;
- GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
- switch (ResetInfo->ResetId)
- {
- case 4:
- switch (ResetInfo->ResetControl)
- {
- case AssertSlotReset:
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
- Data8 &= ~(UINT8)BIT6 ;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
- Status = AGESA_SUCCESS;
- break;
- case DeassertSlotReset:
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
- Data8 |= BIT6 ;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
- Status = AGESA_SUCCESS;
- break;
- }
- break;
- case 6:
- switch (ResetInfo->ResetControl)
- {
- case AssertSlotReset:
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
- Data8 &= ~(UINT8)BIT6 ;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
- Status = AGESA_SUCCESS;
- break;
- case DeassertSlotReset:
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
- Data8 |= BIT6 ;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
- Status = AGESA_SUCCESS;
- break;
- }
- break;
- case 7:
- switch (ResetInfo->ResetControl)
- {
- case AssertSlotReset:
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
- Data8 &= ~(UINT8)BIT6 ;
- Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
- Status = AGESA_SUCCESS;
- break;
- case DeassertSlotReset:
- Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
- Data8 |= BIT6 ;
- Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
- Status = AGESA_SUCCESS;
- break;
- }
- break;
- }
- return Status;
+ return AGESA_UNSUPPORTED;
}
diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.h b/src/mainboard/asrock/e350m1/BiosCallOuts.h
index 85aad33e0b..ac404102f7 100644
--- a/src/mainboard/asrock/e350m1/BiosCallOuts.h
+++ b/src/mainboard/asrock/e350m1/BiosCallOuts.h
@@ -66,12 +66,5 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
/* PCIE slot reset control */
AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
-#define SB_GPIO_REG02 2
-#define SB_GPIO_REG09 9
-#define SB_GPIO_REG10 10
-#define SB_GPIO_REG15 15
-#define SB_GPIO_REG17 17
-#define SB_GPIO_REG21 21
-#define SB_GPIO_REG25 25
-#define SB_GPIO_REG28 28
+
#endif //_BIOS_CALLOUT_H_
diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c
index e9b3ee0525..a58056745e 100644
--- a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c
+++ b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c
@@ -59,26 +59,26 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
{
0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
- PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
+ PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0)
},
#if 1
// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
{
0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
- PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5)
+ PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0)
},
// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
{
0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
- PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
+ PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0)
},
// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
- PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
+ PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0)
},
#endif
// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)