asrock/imb-a180: Switch away from ROMCC_BOOTBLOCK

Change-Id: I603e6c83d72cf6c1d8f8c6eef652fdf954a3a284
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37453
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 0 insertions, 60 deletions

diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
deleted file mode 100644
index 5b9a2263e5..0000000000
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pci_ops.h>
-
-#include <northbridge/amd/agesa/state_machine.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
-
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627uhg/w83627uhg.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1)
-
-void board_BeforeAgesa(struct sysinfo *cb)
-{
-	volatile u32 *addr32;
-	u32 t32;
-
-	/* Set LPC decode enables. */
-	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
-	pci_write_config32(dev, 0x44, 0xff03ffd5);
-
-	/* Enable the AcpiMmio space */
-	outb(0x24, 0xcd6);
-	outb(0x1, 0xcd7);
-
-	/* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */
-	outb(0xea, 0xcd6);
-	outb(0x1, 0xcd7);
-
-	/* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */
-	addr32 = (u32 *)0xfed80e28;
-	t32 = *addr32;
-	t32 &= 0xfff8ffff;
-	*addr32 = t32;
-
-	/* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */
-	addr32 = (u32 *)0xfed80e40;
-	t32 = *addr32;
-	t32 &= 0xffffbffb;
-	*addr32 = t32;
-
-	/* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */
-	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-}