diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-19 16:54:06 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-23 10:12:02 +0000 |
| commit | d893a2635fdd02e3fc12021aa4b0200a30d5a0de (patch) | |
| tree | c0930430dfa687eb4ca7f0f6a92d6c6cdfce7150 /src/mainboard/asrock/h81m-hds/romstage.c | |
| parent | 63bc18e3285bf00d3239d89bc0c4cad97cbbc383 (diff) | |
sb/intel/lynxpoint: Enable LPC/SIO setup in bootblock
This allows for serial console during the bootblock and enables
console in general for the bootblock.
Change-Id: I5c6e107c267a7acb5bf9cbeb54eb5361af3b6db4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30315
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asrock/h81m-hds/romstage.c')
| -rw-r--r-- | src/mainboard/asrock/h81m-hds/romstage.c | 31 |
1 files changed, 0 insertions, 31 deletions
diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index a917722306..3af82f2907 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -23,8 +23,6 @@ #include <northbridge/intel/haswell/pei_data.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/lynxpoint/pch.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct6776/nct6776.h> static const struct rcba_config_instruction rcba_config[] = { RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), @@ -41,35 +39,6 @@ static const struct rcba_config_instruction rcba_config[] = { RCBA_END_CONFIG, }; -void mainboard_config_superio(void) -{ - const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); - const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1); - const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI); - const pnp_devfn_t IR_DEV = PNP_DEV(0x2e, NCT6776_SP2); - - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); - - /* Select HWM/LED functions instead of floppy functions. */ - pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03); - pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24); - - /* Power RAM in S3 and let the PCH handle power failure actions. */ - pnp_set_logical_device(ACPI_DEV); - pnp_write_config(ACPI_DEV, 0xe4, 0x70); - - /* - * Don't know what's needed here, just set the same as the vendor - * firmware. - */ - pnp_set_logical_device(IR_DEV); - pnp_write_config(IR_DEV, 0xf1, 0x5c); - - nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); -} - void mainboard_romstage_entry(unsigned long bist) { struct pei_data pei_data = { |