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authorMichael Niewöhner <foss@mniewoehner.de>2020-10-02 18:28:22 +0200
committerMichael Niewöhner <foss@mniewoehner.de>2020-11-13 17:32:37 +0000
commita1843d8411d3caebd0600421c2b6a4c6b0588c19 (patch)
treed1baeb97ea1ca28ca09df0ceb3edd53ef0eea029 /src/mainboard/asrock/h110m
parent8a64ad09a100adf478d65e42e4cc10a18ccc2d16 (diff)
soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig
Select `PM_ACPI_TIMER_OPTIONAL` to enable the new PM ACPI Kconfig and set the FSP option for PM ACPI timer enablement from its value instead of using the old devicetree option. Also drop the obsolete devicetree option from soc code and from the mainboards and add a corresponding Kconfig entry instead. Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45955 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asrock/h110m')
-rw-r--r--src/mainboard/asrock/h110m/devicetree.cb1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index 57acd33570..909c050412 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -24,7 +24,6 @@ chip soc/intel/skylake
# FSP Configuration
register "PrimaryDisplay" = "Display_PEG"
register "SaGv" = "SaGv_Enabled"
- register "PmTimerDisabled" = "0"
# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s