diff options
| author | Martin Roth <martinroth@google.com> | 2017-11-22 19:06:38 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-11-28 00:59:53 +0000 |
| commit | 320b41b148eecfd342e27ea250fbf73915f579bf (patch) | |
| tree | 780fd08b30cbb79b40aa953289ad5ae8c9ad2a97 /src/mainboard/asrock/g41c-gs/devicetree.cb | |
| parent | 73031bcce071f6e760cc0655200dd3be2f39c8b7 (diff) | |
mainboard/google/kahlee: Update chromeos.fmd
- Remove SI_ALL section. This is no longer needed as the PSP dirctory
is placed into the RO coreboot section.
- Add 1MB Legacy section.
- Add Memory cache section. These sections are called "MRC", which is
an Intel term, but AMD platforms will use the same regions for saving
the same sort of data.
BUG=b:65497959, b:67035984
TEST=Build & boot kahlee
Change-Id: I5e41a0aa6bd4b29b8014c6559126a29cd7ed45d8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/mainboard/asrock/g41c-gs/devicetree.cb')
0 files changed, 0 insertions, 0 deletions