mainboard: Add ASRock G41C-GS

Start-point is Gigabyte GA-G41M-ES2L.

This board features a G41 northbridge and an ICH7 southbridge. This
board has slots for both DDR2 and DDR3 (cannot run concurrently
though) but only DDR2 is implemented in coreboot. The SPI flash
resides in a DIP-8 socket.

Tested and working:
* DDR2 dual channel (PC2 5300 and PC2 6400, though raminit is picky
  with assymetric dimm setups);
* 3,5" IDE;
* SATA;
* PCIe x16 (with some patches up for review);
* Uart, PS2 Keyboard;
* USB, ethernet, audio;
* Native graphic init;
* Fan control;
* Reboot, poweroff, S3 resume;
* Flashrom (vendor and coreboot).

Tested but fails:
* DDR3 (not implemented in coreboot).

Tests were run with SeaBIOS and Debian sid, using Linux 4.9.0.

Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

5 files changed, 149 insertions, 0 deletions

diff --git a/src/mainboard/asrock/g41c-gs/acpi/ec.asl b/src/mainboard/asrock/g41c-gs/acpi/ec.asl
new file mode 100644
index 0000000000..2997587d82
--- /dev/null
+++ b/src/mainboard/asrock/g41c-gs/acpi/ec.asl
@@ -0,0 +1 @@
+/* dummy */
diff --git a/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl b/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000000..bb8745ee97
--- /dev/null
+++ b/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This is board specific information:
+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+	Return (Package() {
+		/* PCI1 SLOT 1 */
+		Package() { 0x0001ffff, 0, 0, 0x16},
+		Package() { 0x0001ffff, 1, 0, 0x17},
+		Package() { 0x0001ffff, 2, 0, 0x14},
+		Package() { 0x0001ffff, 3, 0, 0x15},
+
+		/* PCI1 SLOT 2 */
+		Package() { 0x0002ffff, 0, 0, 0x17},
+		Package() { 0x0002ffff, 1, 0, 0x14},
+		Package() { 0x0002ffff, 2, 0, 0x15},
+		Package() { 0x0002ffff, 3, 0, 0x16},
+
+		/* device not in lspci but in vendor DSDT */
+		/* Package() { 0x0008ffff, 0, 0, 0x14}, */
+	})
+} Else {
+	Return (Package() {
+		Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKH, 0},
+		Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKE, 0},
+		Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKF, 0},
+
+		Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKH, 0},
+		Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},
+		Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKF, 0},
+		Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKG, 0},
+
+		/* device not in lspci but in vendor DSDT */
+		/* Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, */
+	})
+}
diff --git a/src/mainboard/asrock/g41c-gs/acpi/platform.asl b/src/mainboard/asrock/g41c-gs/acpi/platform.asl
new file mode 100644
index 0000000000..6c92a4ed47
--- /dev/null
+++ b/src/mainboard/asrock/g41c-gs/acpi/platform.asl
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Method(_PIC, 1)
+{
+	/* Remember the OS' IRQ routing choice.  */
+	Store(Arg0, PICM)
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	/* SMI Function */
+	Store (0, TRP0)		/* Generate trap */
+	Return (SMIF)		/* Return value of SMI handler */
+}
diff --git a/src/mainboard/asrock/g41c-gs/acpi/superio.asl b/src/mainboard/asrock/g41c-gs/acpi/superio.asl
new file mode 100644
index 0000000000..2997587d82
--- /dev/null
+++ b/src/mainboard/asrock/g41c-gs/acpi/superio.asl
@@ -0,0 +1 @@
+/* dummy */
diff --git a/src/mainboard/asrock/g41c-gs/acpi/x4x_pci_irqs.asl b/src/mainboard/asrock/g41c-gs/acpi/x4x_pci_irqs.asl
new file mode 100644
index 0000000000..5bec150f0b
--- /dev/null
+++ b/src/mainboard/asrock/g41c-gs/acpi/x4x_pci_irqs.asl
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* This is board specific information: IRQ routing for x4x */
+
+/* PCI Interrupt Routing */
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			/* PEG */
+			Package() { 0x0001ffff, 0, 0, 0x10 },
+			/* Internal GFX */
+			Package() { 0x0002ffff, 0, 0, 0x10 },
+			/* High Definition Audio	0:1b.0 */
+			Package() { 0x001bffff, 0, 0, 0x10 },
+			/* PCIe Root Ports		0:1c.x */
+			Package() { 0x001cffff, 0, 0, 0x10 },
+			Package() { 0x001cffff, 1, 0, 0x11 },
+			Package() { 0x001cffff, 2, 0, 0x12 },
+			Package() { 0x001cffff, 3, 0, 0x13 },
+			/* USB and EHCI			0:1d.x */
+			Package() { 0x001dffff, 0, 0, 0x17 },
+			Package() { 0x001dffff, 1, 0, 0x13 },
+			Package() { 0x001dffff, 2, 0, 0x12 },
+			Package() { 0x001dffff, 3, 0, 0x10 },
+			/* PATA/SATA/SMBUS		0:1f.1-3 */
+			Package() { 0x001fffff, 0, 0, 0x12 },
+			Package() { 0x001fffff, 1, 0, 0x13 },
+		})
+	} Else {
+		Return (Package() {
+			/* PEG */
+			Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			/* Internal GFX */
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			/* High Definition Audio	0:1b.0 */
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			/* PCIe Root Ports		0:1c.x */
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+			/* USB and EHCI			0:1d.x */
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+			/* PATA/SATA/SMBUS		0:1f.1-3 */
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+		})
+	}
+}