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authorArthur Heymans <arthur@aheymans.xyz>2017-03-18 15:54:42 +0100
committerMartin Roth <martinroth@google.com>2017-05-13 17:37:27 +0200
commit7d46e96ed78ca1af7c951f79c16e6193f0ee094e (patch)
tree7b4d3ea31b737b79be30c60dc68885018d7e493a /src/mainboard/asrock/g41c-gs/Makefile.inc
parentcfd433b96daa2d2f7f4f99fff7608e110b64dca4 (diff)
mainboard: Add ASRock G41C-GS
Start-point is Gigabyte GA-G41M-ES2L. This board features a G41 northbridge and an ICH7 southbridge. This board has slots for both DDR2 and DDR3 (cannot run concurrently though) but only DDR2 is implemented in coreboot. The SPI flash resides in a DIP-8 socket. Tested and working: * DDR2 dual channel (PC2 5300 and PC2 6400, though raminit is picky with assymetric dimm setups); * 3,5" IDE; * SATA; * PCIe x16 (with some patches up for review); * Uart, PS2 Keyboard; * USB, ethernet, audio; * Native graphic init; * Fan control; * Reboot, poweroff, S3 resume; * Flashrom (vendor and coreboot). Tested but fails: * DDR3 (not implemented in coreboot). Tests were run with SeaBIOS and Debian sid, using Linux 4.9.0. Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/asrock/g41c-gs/Makefile.inc')
-rw-r--r--src/mainboard/asrock/g41c-gs/Makefile.inc2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/asrock/g41c-gs/Makefile.inc b/src/mainboard/asrock/g41c-gs/Makefile.inc
new file mode 100644
index 0000000000..f3d7e76263
--- /dev/null
+++ b/src/mainboard/asrock/g41c-gs/Makefile.inc
@@ -0,0 +1,2 @@
+ramstage-y += cstates.c
+romstage-y += gpio.c