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authorKerry Sheh <shekairui@gmail.com>2011-12-22 12:18:26 +0800
committerMarc Jones <marcj303@gmail.com>2012-01-02 23:13:50 +0100
commit28f171096bc289f848c03593a6d04c2987c89617 (patch)
tree86adffc82f7120ac3be7ca426a5b5e5b7f170465 /src/mainboard/asrock/e350m1
parentd6ed09b7eca40a29a2cd4a3b6a5f0e4dfeb07641 (diff)
F14 mainboard: mptable update
Add GNB internal graphic interrupt, correct southbridge hd audio device interrupt. and remove the dead code already commented out. south_station, union_station, inagua, persimmon and e350m1 mainboard are included herein. Change-Id: Ic7618d80e0432ed0e22d1c16e1adb8ba6cea2e59 Signed-off-by: Kerry Sheh <shekairui@gmail.com> Signed-off-by: Kerry Sheh <kerry.she@amd.com> Reviewed-on: http://review.coreboot.org/451 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/mainboard/asrock/e350m1')
-rw-r--r--src/mainboard/asrock/e350m1/mptable.c8
1 files changed, 5 insertions, 3 deletions
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index 960c2c86f1..de9d7f4c64 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -90,9 +90,13 @@ static void *smp_write_config_table(void *v)
#define PCI_INT(bus, dev, fn, pin)
#endif
+ /* APU Internal Graphic Device*/
+ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* HD Audio: */
+ /* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
@@ -105,8 +109,6 @@ static void *smp_write_config_table(void *v)
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
- /* PCI_INT(0x0, 0x14, 0x2, 0x12); */
-
/* on board NIC & Slot PCIE. */
/* PCI slots */