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authorKerry She <shekairui@gmail.com>2011-08-18 18:44:00 +0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2011-09-07 01:10:05 +0200
commit6209c8299a4bdcdb51cd6bf0c43c571ed575ad96 (patch)
tree843a812c073191dd08315f3a4791f0b66480208d /src/mainboard/asrock/e350m1
parentfeed329a0c006968242aa3065506b5f37f4308d4 (diff)
AMD SB800 southbridge update
This patch enables access to the registers of the hardware monitor logical device in the superio via isa ports 0x295/0x296. Previously this was not enabled in the SB8xx LPC device. This is required for initialisation in init_hwm() in src/superio/winbond/w83627hf/superio.c and also by OS-level sensor monitoring such as lm-sensors to access temperature, fan monitoring and control and voltage registers. asrock/e350m1 and advansus/a785e-i mainboard changes are included herein. Change-Id: I2176885549277b335c0c41b48457d09b9b76b703 Signed-off-by: Per Hansen <perh52@runbox.com> Signed-off-by: Kerry She <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/159 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/asrock/e350m1')
-rw-r--r--src/mainboard/asrock/e350m1/Kconfig1
-rw-r--r--src/mainboard/asrock/e350m1/platform_cfg.h5
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig
index c60f6dfca4..802b58f37b 100644
--- a/src/mainboard/asrock/e350m1/Kconfig
+++ b/src/mainboard/asrock/e350m1/Kconfig
@@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_AMD_AGESA_FAMILY14
select SOUTHBRIDGE_AMD_CIMX_SB800
select SUPERIO_WINBOND_W83627HF
+ select SB_SUPERIO_HWM
select BOARD_HAS_FADT
select HAVE_BUS_CONFIG
select HAVE_OPTION_TABLE
diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h
index 6e0faea633..326765162e 100644
--- a/src/mainboard/asrock/e350m1/platform_cfg.h
+++ b/src/mainboard/asrock/e350m1/platform_cfg.h
@@ -219,4 +219,9 @@
*/
#define GEC_CONFIG 0
+/**
+ * @def SIO_HWM_BASE_ADDRESS Super IO HWM base address
+ */
+#define SIO_HWM_BASE_ADDRESS 0x290
+
#endif