ASRock DSDT: Split the ASRock DSDT

This is the same split as was done on the Persimmon.

Change-Id: I25bd63f23417b7926232f07eaaa7917170af9d60
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/3050
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

7 files changed, 507 insertions, 0 deletions

diff --git a/src/mainboard/asrock/e350m1/acpi/gpe.asl b/src/mainboard/asrock/e350m1/acpi/gpe.asl
new file mode 100644
index 0000000000..ac70b04af5
--- /dev/null
+++ b/src/mainboard/asrock/e350m1/acpi/gpe.asl
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Scope(\_GPE) {	/* Start Scope GPE */
+
+	/*  General event 3  */
+	Method(_L03) {
+		/* DBGO("\\_GPE\\_L00\n") */
+		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+
+	/*  Legacy PM event  */
+	Method(_L08) {
+		/* DBGO("\\_GPE\\_L08\n") */
+	}
+
+	/*  Temp warning (TWarn) event  */
+	Method(_L09) {
+		/* DBGO("\\_GPE\\_L09\n") */
+		/* Notify (\_TZ.TZ00, 0x80) */
+	}
+
+	/*  USB controller PME#  */
+	Method(_L0B) {
+		/* DBGO("\\_GPE\\_L0B\n") */
+		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+
+	/*  ExtEvent0 SCI event  */
+	Method(_L10) {
+		/* DBGO("\\_GPE\\_L10\n") */
+	}
+
+
+	/*  ExtEvent1 SCI event  */
+	Method(_L11) {
+		/* DBGO("\\_GPE\\_L11\n") */
+	}
+
+	/*  GPIO0 or GEvent8 event  */
+	Method(_L18) {
+		/* DBGO("\\_GPE\\_L18\n") */
+		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+
+	/*  Azalia SCI event  */
+	Method(_L1B) {
+		/* DBGO("\\_GPE\\_L1B\n") */
+		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+
+} 	/* End Scope GPE */
+
+/* Contains the GPEs for USB overcurrent */
+#include "usb_oc.asl"
+
diff --git a/src/mainboard/asrock/e350m1/acpi/mainboard.asl b/src/mainboard/asrock/e350m1/acpi/mainboard.asl
new file mode 100644
index 0000000000..1ec881c7e8
--- /dev/null
+++ b/src/mainboard/asrock/e350m1/acpi/mainboard.asl
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Data to be patched by the BIOS during POST */
+/* FIXME the patching is not done yet! */
+/* Memory related values */
+Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
+Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+Name(PBLN, 0x0)	/* Length of BIOS area */
+
+Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)	/* Base address of PCIe config space */
+Name(HPBA, 0xFED00000)	/* Base address of HPET table */
+
+Name(SSFG, 0x0D)	/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+/* Some global data */
+Name(OSTP, 3)	/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+Name(OSV, Ones)	/* Assume nothing */
+Name(PMOD, One)	/* Assume APIC */
+
+Scope(\_SB) {
+	Method(CkOT, 0){
+
+		if(LNotEqual(OSTP, Ones)) {Return(OSTP)}	/* OS version was already detected */
+
+		if(CondRefOf(\_OSI,Local1))
+		{
+			Store(1, OSTP)					/* Assume some form of XP */
+			if (\_OSI("Windows 2006"))		/* Vista */
+			{
+				Store(2, OSTP)
+			}
+		} else {
+			If(WCMP(\_OS,"Linux")) {
+				Store(3, OSTP)				/* Linux */
+			} Else {
+				Store(4, OSTP)				/* Gotta be WinCE */
+			}
+		}
+		Return(OSTP)
+	}
+}
+
+Scope(\_SI) {
+	Method(_SST, 1) {
+		/* DBGO("\\_SI\\_SST\n") */
+		/* DBGO("   New Indicator state: ") */
+		/* DBGO(Arg0) */
+		/* DBGO("\n") */
+	}
+} /* End Scope SI */
diff --git a/src/mainboard/asrock/e350m1/acpi/sleep.asl b/src/mainboard/asrock/e350m1/acpi/sleep.asl
new file mode 100644
index 0000000000..a109151509
--- /dev/null
+++ b/src/mainboard/asrock/e350m1/acpi/sleep.asl
@@ -0,0 +1,121 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+* \_PTS - Prepare to Sleep method
+*
+*	Entry:
+*		Arg0=The value of the sleeping state S1=1, S2=2, etc
+*
+* Exit:
+*		-none-
+*
+* The _PTS control method is executed at the beginning of the sleep process
+* for S1-S5. The sleeping value is passed to the _PTS control method.	This
+* control method may be executed a relatively long time before entering the
+* sleep state and the OS may abort	the operation without notification to
+* the ACPI driver.  This method cannot modify the configuration or power
+* state of any device in the system.
+*/
+Method(\_PTS, 1) {
+	/* DBGO("\\_PTS\n") */
+	/* DBGO("From S0 to S") */
+	/* DBGO(Arg0) */
+	/* DBGO("\n") */
+
+	/* Don't allow PCIRST# to reset USB */
+	if (LEqual(Arg0,3)){
+		Store(0,URRE)
+	}
+
+	/* Clear sleep SMI status flag and enable sleep SMI trap. */
+	/*Store(One, CSSM)
+	Store(One, SSEN)*/
+
+	/* On older chips, clear PciExpWakeDisEn */
+	/*if (LLessEqual(\_SB.SBRI, 0x13)) {
+	*    	Store(0,\_SB.PWDE)
+	*}
+	*/
+
+	/* Clear wake status structure. */
+	Store(0, Index(WKST,0))
+	Store(0, Index(WKST,1))
+} /* End Method(\_PTS) */
+
+/*
+*	\_BFS OEM Back From Sleep method
+*
+*	Entry:
+*		Arg0=The value of the sleeping state S1=1, S2=2
+*
+*	Exit:
+*		-none-
+*/
+Method(\_BFS, 1) {
+	/* DBGO("\\_BFS\n") */
+	/* DBGO("From S") */
+	/* DBGO(Arg0) */
+	/* DBGO(" to S0\n") */
+}
+
+/*
+*  \_WAK System Wake method
+*
+*	Entry:
+*		Arg0=The value of the sleeping state S1=1, S2=2
+*
+*	Exit:
+*		Return package of 2 DWords
+*		Dword 1 - Status
+*			0x00000000	wake succeeded
+*			0x00000001	Wake was signaled but failed due to lack of power
+*			0x00000002	Wake was signaled but failed due to thermal condition
+*		Dword 2 - Power Supply state
+*			if non-zero the effective S-state the power supply entered
+*/
+Method(\_WAK, 1) {
+	/* DBGO("\\_WAK\n") */
+	/* DBGO("From S") */
+	/* DBGO(Arg0) */
+	/* DBGO(" to S0\n") */
+
+	/* Re-enable HPET */
+	Store(1,HPDE)
+
+	/* Restore PCIRST# so it resets USB */
+	if (LEqual(Arg0,3)){
+		Store(1,URRE)
+	}
+
+	/* Arbitrarily clear PciExpWakeStatus */
+	Store(PWST, PWST)
+
+	/* if(DeRefOf(Index(WKST,0))) {
+	*	Store(0, Index(WKST,1))
+	* } else {
+	*	Store(Arg0, Index(WKST,1))
+	* }
+	*/
+	Return(WKST)
+} /* End Method(\_WAK) */
+
diff --git a/src/mainboard/asrock/e350m1/acpi/smbus.asl b/src/mainboard/asrock/e350m1/acpi/smbus.asl
new file mode 100644
index 0000000000..e4ccfe3467
--- /dev/null
+++ b/src/mainboard/asrock/e350m1/acpi/smbus.asl
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* SMBUS Support */
+Mutex (SBX0, 0x00)
+OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
+	Field (SMB0, ByteAcc, NoLock, Preserve) {
+		HSTS,   8,  /* SMBUS status */
+		SSTS,   8,  /* SMBUS slave status */
+		HCNT,   8,  /* SMBUS control */
+		HCMD,   8,  /* SMBUS host cmd */
+		HADD,   8,  /* SMBUS address */
+		DAT0,   8,  /* SMBUS data0 */
+		DAT1,   8,  /* SMBUS data1 */
+		BLKD,   8,  /* SMBUS block data */
+		SCNT,   8,  /* SMBUS slave control */
+		SCMD,   8,  /* SMBUS shaow cmd */
+		SEVT,   8,  /* SMBUS slave event */
+		SDAT,   8   /* SMBUS slave data */
+}
+
+Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
+	Store (0x1E, HSTS)
+	Store (0xFA, Local0)
+	While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
+		Stall (0x64)
+		Decrement (Local0)
+	}
+
+	Return (Local0)
+}
+
+Method (SWTC, 1, NotSerialized) {
+	Store (Arg0, Local0)
+	Store (0x07, Local2)
+	Store (One, Local1)
+	While (LEqual (Local1, One)) {
+		Store (And (HSTS, 0x1E), Local3)
+		If (LNotEqual (Local3, Zero)) { /* read sucess */
+			If (LEqual (Local3, 0x02)) {
+				Store (Zero, Local2)
+			}
+
+			Store (Zero, Local1)
+		}
+		Else {
+			If (LLess (Local0, 0x0A)) { /* read failure */
+				Store (0x10, Local2)
+				Store (Zero, Local1)
+			}
+			Else {
+				Sleep (0x0A) /* 10 ms, try again */
+				Subtract (Local0, 0x0A, Local0)
+			}
+		}
+	}
+
+	Return (Local2)
+}
+
+Method (SMBR, 3, NotSerialized) {
+	Store (0x07, Local0)
+	If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
+		Store (WCLR (), Local0) /* clear SMBUS status register before read data */
+		If (LEqual (Local0, Zero)) {
+			Release (SBX0)
+			Return (0x0)
+		}
+
+		Store (0x1F, HSTS)
+		Store (Or (ShiftLeft (Arg1, One), One), HADD)
+		Store (Arg2, HCMD)
+		If (LEqual (Arg0, 0x07)) {
+			Store (0x48, HCNT) /* read byte */
+		}
+
+		Store (SWTC (0x03E8), Local1) /* 1000 ms */
+		If (LEqual (Local1, Zero)) {
+			If (LEqual (Arg0, 0x07)) {
+				Store (DAT0, Local0)
+			}
+		}
+		Else {
+			Store (Local1, Local0)
+		}
+
+		Release (SBX0)
+	}
+
+	/* DBGO("the value of SMBusData0 register ") */
+	/* DBGO(Arg2) */
+	/* DBGO(" is ") */
+	/* DBGO(Local0) */
+	/* DBGO("\n") */
+
+	Return (Local0)
+}
+
diff --git a/src/mainboard/asrock/e350m1/acpi/superio.asl b/src/mainboard/asrock/e350m1/acpi/superio.asl
new file mode 100644
index 0000000000..7d8d9df38c
--- /dev/null
+++ b/src/mainboard/asrock/e350m1/acpi/superio.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* No SuperIO device or functionality yet */
diff --git a/src/mainboard/asrock/e350m1/acpi/thermal.asl b/src/mainboard/asrock/e350m1/acpi/thermal.asl
new file mode 100644
index 0000000000..ec1fbf06dc
--- /dev/null
+++ b/src/mainboard/asrock/e350m1/acpi/thermal.asl
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* THERMAL */
+Scope(\_TZ) {
+	Name (KELV, 2732)
+	Name (THOT, 800)
+	Name (TCRT, 850)
+
+	ThermalZone(TZ00) {
+		Method(_AC0,0) {	/* Active Cooling 0 (0=highest fan speed) */
+			/* DBGO("\\_TZ\\TZ00\\_AC0\n") */
+			Return(Add(0, 2730))
+		}
+		Method(_AL0,0) {	/* Returns package of cooling device to turn on */
+			/* DBGO("\\_TZ\\TZ00\\_AL0\n") */
+			Return(Package() {\_TZ.TZ00.FAN0})
+		}
+		Device (FAN0) {
+			Name(_HID, EISAID("PNP0C0B"))
+			Name(_PR0, Package() {PFN0})
+		}
+
+		PowerResource(PFN0,0,0) {
+			Method(_STA) {
+				Store(0xF,Local0)
+				Return(Local0)
+			}
+			Method(_ON) {
+				/* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
+			}
+			Method(_OFF) {
+				/* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
+			}
+		}
+
+		Method(_HOT,0) {	/* return hot temp in tenths degree Kelvin */
+			/* DBGO("\\_TZ\\TZ00\\_HOT\n") */
+			Return (Add (THOT, KELV))
+		}
+		Method(_CRT,0) {	/* return critical temp in tenths degree Kelvin */
+			/* DBGO("\\_TZ\\TZ00\\_CRT\n") */
+			Return (Add (TCRT, KELV))
+		}
+		Method(_TMP,0) {	/* return current temp of this zone */
+			Store (SMBR (0x07, 0x4C,, 0x00), Local0)
+			If (LGreater (Local0, 0x10)) {
+				Store (Local0, Local1)
+			}
+			Else {
+				Add (Local0, THOT, Local0)
+				Return (Add (400, KELV))
+			}
+
+			Store (SMBR (0x07, 0x4C, 0x01), Local0)
+			/* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
+			/* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
+			If (LGreater (Local0, 0x10)) {
+				If (LGreater (Local0, Local1)) {
+					Store (Local0, Local1)
+				}
+
+				Multiply (Local1, 10, Local1)
+				Return (Add (Local1, KELV))
+			}
+			Else {
+				Add (Local0, THOT, Local0)
+				Return (Add (400 , KELV))
+			}
+		} /* end of _TMP */
+	} /* end of TZ00 */
+}
diff --git a/src/mainboard/asrock/e350m1/acpi/usb.asl b/src/mainboard/asrock/e350m1/acpi/usb_oc.asl
index 2822ffda83..d79d64eb1a 100644
--- a/src/mainboard/asrock/e350m1/acpi/usb.asl
+++ b/src/mainboard/asrock/e350m1/acpi/usb_oc.asl
@@ -25,6 +25,19 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
 		#include "usb.asl"
 	}
 */
+
+/* USB overcurrent mapping pins.   */
+Name(UOM0, 0)
+Name(UOM1, 2)
+Name(UOM2, 0)
+Name(UOM3, 7)
+Name(UOM4, 2)
+Name(UOM5, 2)
+Name(UOM6, 6)
+Name(UOM7, 2)
+Name(UOM8, 6)
+Name(UOM9, 6)
+
 Method(UCOC, 0) {
 	Sleep(20)
     	Store(0x13,CMTI)