Add support for the ASRock E350M1, an AMD family 14h Fusion board.

A video option rom must be added for UMA graphics support. It can
be extracted from the supplied UEFI BIOS.

ASRock E350M1 support is based on the AMD persimmon project. The
major differences are SIO model and DIMM SDP addressing. With this
coreboot and seabios, the board can boot DOS from a SATA drive and
can boot WinPE from a USB flash drive. I was unable to get
Windows setup to run.

The board has a socketed SPI flash BIOS chip and a serial port
header. The SIO is Nuvoton NCT5572D. Using coreboot's existing
Winbond w83627hf is a good enough match to get the serial port
and keyboard working.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6382 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

4 files changed, 0 insertions, 337 deletions

diff --git a/src/mainboard/asrock/e350m1/acpi/ssdt2.asl b/src/mainboard/asrock/e350m1/acpi/ssdt2.asl
deleted file mode 100644
index ef1a4bf9eb..0000000000
--- a/src/mainboard/asrock/e350m1/acpi/ssdt2.asl
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
-	Scope (_SB)
-	{
-		External (DADD, MethodObj)
-		External (GHCE, MethodObj)
-		External (GHCN, MethodObj)
-		External (GHCL, MethodObj)
-		External (GHCD, MethodObj)
-		External (GNUS, MethodObj)
-		External (GIOR, MethodObj)
-		External (GMEM, MethodObj)
-		External (GWBN, MethodObj)
-		External (GBUS, MethodObj)
-
-		External (PICF)
-
-		External (\_SB.PCI0.LNKA, DeviceObj)
-		External (\_SB.PCI0.LNKB, DeviceObj)
-		External (\_SB.PCI0.LNKC, DeviceObj)
-		External (\_SB.PCI0.LNKD, DeviceObj)
-
-		Device (PCIX)
-		{
-
-		// BUS ? Second HT Chain
-		Name (HCIN, 0xcc)  // HC2 0x01
-
-		Name (_UID,	 0xdd)	// HC 0x03
-
-		Name (_HID, "PNP0A03")
-
-		Method (_ADR, 0, NotSerialized) //Fake bus should be 0
-		{
-			Return (DADD(GHCN(HCIN), 0x00000000))
-		}
-
-		Method (_BBN, 0, NotSerialized)
-		{
-			 Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
-		}
-
-		Method (_STA, 0, NotSerialized)
-		{
-			Return (\_SB.GHCE(HCIN))
-		}
-
-		Method (_CRS, 0, NotSerialized)
-		{
-			Name (BUF0, ResourceTemplate () { })
-			Store( GHCN(HCIN), Local4)
-			Store( GHCL(HCIN), Local5)
-
-			Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
-			Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
-			Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
-			Return (Local3)
-		}
-
-			#include "acpi/pci2_hc.asl"
-		}
-	}
-
-}
-
diff --git a/src/mainboard/asrock/e350m1/acpi/ssdt3.asl b/src/mainboard/asrock/e350m1/acpi/ssdt3.asl
deleted file mode 100644
index 68a4b95abe..0000000000
--- a/src/mainboard/asrock/e350m1/acpi/ssdt3.asl
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
-	Scope (_SB)
-	{
-		External (DADD, MethodObj)
-		External (GHCE, MethodObj)
-		External (GHCN, MethodObj)
-		External (GHCL, MethodObj)
-		External (GHCD, MethodObj)
-		External (GNUS, MethodObj)
-		External (GIOR, MethodObj)
-		External (GMEM, MethodObj)
-		External (GWBN, MethodObj)
-		External (GBUS, MethodObj)
-
-		External (PICF)
-
-		External (\_SB.PCI0.LNKA, DeviceObj)
-		External (\_SB.PCI0.LNKB, DeviceObj)
-		External (\_SB.PCI0.LNKC, DeviceObj)
-		External (\_SB.PCI0.LNKD, DeviceObj)
-
-		Device (PCIX)
-		{
-
-			// BUS ? Second HT Chain
-			Name (HCIN, 0xcc)  // HC2 0x01
-
-			Name (_UID,	 0xdd)	// HC 0x03
-
-			Name (_HID, "PNP0A03")
-
-			Method (_ADR, 0, NotSerialized) //Fake bus should be 0
-			{
-				Return (DADD(GHCN(HCIN), 0x00000000))
-			}
-
-			Method (_BBN, 0, NotSerialized)
-			{
-				Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
-			}
-
-			Method (_STA, 0, NotSerialized)
-			{
-				Return (\_SB.GHCE(HCIN))
-			}
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				Name (BUF0, ResourceTemplate () { })
-				Store( GHCN(HCIN), Local4)
-				Store( GHCL(HCIN), Local5)
-
-				Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
-				Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
-				Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
-				Return (Local3)
-			}
-
-			#include "acpi/pci3_hc.asl"
-		}
-	}
-
-}
-
diff --git a/src/mainboard/asrock/e350m1/acpi/ssdt4.asl b/src/mainboard/asrock/e350m1/acpi/ssdt4.asl
deleted file mode 100644
index e06fe8ab85..0000000000
--- a/src/mainboard/asrock/e350m1/acpi/ssdt4.asl
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
-	Scope (_SB)
-	{
-		External (DADD, MethodObj)
-		External (GHCE, MethodObj)
-		External (GHCN, MethodObj)
-		External (GHCL, MethodObj)
-		External (GHCD, MethodObj)
-		External (GNUS, MethodObj)
-		External (GIOR, MethodObj)
-		External (GMEM, MethodObj)
-		External (GWBN, MethodObj)
-		External (GBUS, MethodObj)
-
-		External (PICF)
-
-		External (\_SB.PCI0.LNKA, DeviceObj)
-		External (\_SB.PCI0.LNKB, DeviceObj)
-		External (\_SB.PCI0.LNKC, DeviceObj)
-		External (\_SB.PCI0.LNKD, DeviceObj)
-
-		Device (PCIX)
-		{
-
-			// BUS ? Second HT Chain
-			Name (HCIN, 0xcc)  // HC2 0x01
-
-			Name (_UID,	 0xdd)	// HC 0x03
-
-			Name (_HID, "PNP0A03")
-
-			Method (_ADR, 0, NotSerialized) //Fake bus should be 0
-			{
-				Return (DADD(GHCN(HCIN), 0x00000000))
-			}
-
-			Method (_BBN, 0, NotSerialized)
-			{
-				Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
-			}
-
-			Method (_STA, 0, NotSerialized)
-			{
-				Return (\_SB.GHCE(HCIN))
-			}
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				Name (BUF0, ResourceTemplate () { })
-				Store( GHCN(HCIN), Local4)
-				Store( GHCL(HCIN), Local5)
-
-				Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
-				Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
-				Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
-				Return (Local3)
-			}
-
-			#include "acpi/pci4_hc.asl"
-		}
-	}
-
-}
-
diff --git a/src/mainboard/asrock/e350m1/acpi/ssdt5.asl b/src/mainboard/asrock/e350m1/acpi/ssdt5.asl
deleted file mode 100644
index a141a378d2..0000000000
--- a/src/mainboard/asrock/e350m1/acpi/ssdt5.asl
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-
-DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
-	Scope (_SB)
-	{
-	External (DADD, MethodObj)
-	External (GHCE, MethodObj)
-	External (GHCN, MethodObj)
-	External (GHCL, MethodObj)
-	External (GHCD, MethodObj)
-	External (GNUS, MethodObj)
-	External (GIOR, MethodObj)
-	External (GMEM, MethodObj)
-	External (GWBN, MethodObj)
-	External (GBUS, MethodObj)
-
-	External (PICF)
-
-	External (\_SB.PCI0.LNKA, DeviceObj)
-	External (\_SB.PCI0.LNKB, DeviceObj)
-	External (\_SB.PCI0.LNKC, DeviceObj)
-	External (\_SB.PCI0.LNKD, DeviceObj)
-
-		Device (PCIX)
-		{
-
-			// BUS ? Second HT Chain
-			Name (HCIN, 0xcc)  // HC2 0x01
-
-			Name (_UID,	 0xdd)	// HC 0x03
-
-			Name (_HID, "PNP0A03")
-
-			Method (_ADR, 0, NotSerialized) //Fake bus should be 0
-			{
-				Return (DADD(GHCN(HCIN), 0x00000000))
-			}
-
-			Method (_BBN, 0, NotSerialized)
-			{
-				Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
-			}
-
-			Method (_STA, 0, NotSerialized)
-			{
-				Return (\_SB.GHCE(HCIN))
-			}
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				Name (BUF0, ResourceTemplate () { })
-				Store( GHCN(HCIN), Local4)
-				Store( GHCL(HCIN), Local5)
-
-				Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
-				Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
-				Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
-				Return (Local3)
-			}
-
-			#include "acpi/pci5_hc.asl"
-		}
-	}
-
-}
-